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CITATION

Bianchi, Giovanni. Phase-Locked Loop Synthesizer Simulation. US: McGraw-Hill Professional, 2005.

Phase-Locked Loop Synthesizer Simulation

Authors: Giovanni Bianchi

Published:  March 2005

eISBN: 9780071466899 0071466894 | ISBN: 9780071453714
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  • Terms of Use
  • Want to learn more?
  • Contents
  • Preface
  • Chapter 1. Phase-Locked Loop Basics
  • 1.1 Introduction
  • 1.2 PLL Working Principles
  • 1.3 Laplace and Fourier Transforms
  • 1.3.1 Definitions
  • 1.3.2 Basic Properties
  • 1.3.3 Transforms of Some Important Functions
  • 1.4 PLL Transfer Functions
  • 1.4.1 PLL Stability Analysis
  • 1.5 PLL Order and PLL Type
  • 1.6 First-Order PLL
  • 1.7 Second-Order PLL
  • References
  • Chapter 2. Loop Components
  • 2.1 Introduction
  • 2.2 Phase Detector
  • 2.2.1 Multiplier as Phase Detector
  • 2.2.2 Phase Frequency Detector
  • 2.3 Loop Filter
  • 2.3.1 Reference Spur Filtering
  • 2.3.2 Loop Filters for Voltage Output Phase Detectors
  • 2.3.3 Loop Filters for Charge Pump
  • 2.3.4 Loop Filter Scaling
  • 2.4 VCO
  • 2.4.1 Principle of Working
  • 2.4.2 VCO Analysis
  • 2.4.3 Phase Noise
  • 2.4.4 Pulling and Pushing
  • 2.5 Reference Sources
  • 2.6 Frequency Dividers
  • 2.6.1 Frequency Divider Phase Noise
  • References
  • Chapter 3. Fractional-N Frequency Divider
  • 3.1 Introduction
  • 3.2 Single-Accumulator Fractional Divider
  • 3.3 Multiple-Accumulator Fractional Dividers
  • 3.3.1 Z Transform
  • 3.3.2 First-Order sigma-delta Modulator
  • 3.3.3 Higher-Order sigma-delta Converters
  • 3.3.4 Multiple-Accumulator Fractional-N Phase Noise
  • References
  • Chapter 4. Synthesizer Performance Simulation
  • 4.1 Introduction
  • 4.2 Simulation Techniques
  • 4.3 Phase Noise
  • 4.3.1 Definitions
  • 4.3.2 Phase Noise of PLL Synthesizer
  • 4.4 Modulation of the PLL
  • 4.4.1 Modulation of the Reference Oscillator Only
  • 4.4.2 Modulation of the VCO Only
  • 4.4.3 Dual-Point Modulation
  • 4.5 Settling Time
  • 4.5.1 Lock-In
  • 4.5.2 Pull-In
  • 4.6 Final Note on Circuit-Based Simulation
  • References
  • Chapter 5. Miscellaneous
  • 5.1 Introduction
  • 5.2 PLL Performance Verification
  • 5.2.1 Measurement of PLL Frequency Response Magnitude
  • 5.3 Sampling Phase Detector
  • 5.4 Multiple-Loop PLL
  • 5.4.1 Phase Noise of Multiple-Loop PLL
  • 5.4.2 Transients in Multiple-Loop PLL
  • 5.4.3 Variations on Double-Loop Architecture
  • 5.5 Direct Digital Synthesizer
  • 5.5.1 Principle of DDS Operation
  • 5.5.2 Effects of Nonideal Components on DDS Performance
  • 5.5.3 Enhancements of DDS Architecture
  • References
  • Index