VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition

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VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition

VHDL:Modular Design and Synthesis of Cores and Systems, Third Edition

Authors: Zainalabedin Navabi

Published: April 2007

eISBN: 9780071508926 0071508929 | ISBN: 9780071475457

Contents

Preface

Introduction

Acknowledgments

Chapter 1 Digital System Design Automation with VHDL

1.1 Abstraction Levels

1.2 System Level Design Flow

1.2.1 Hardware/Software Partitioning

1.2.2 Hardware Part

1.2.3 Software Part

1.3 RTL Design Flow

1.3.1 Design Entry

1.3.2 Testbench in VHDL

1.3.3 Design Validation

1.3.4 Compilation and Synthesis

1.3.5 Timing Analysis

1.3.6 Post-Synthesis Simulation

1.3.7 Hardware Generation

1.4 VHDL

1.4.1 VHDL Initiation

1.4.2 Existing Languages

1.4.3 VHDL Requirements

1.4.4 The VHDL Language

1.5 Summary

Problems

Suggested Reading

Chapter 2 RTL Design with VHDL

2.1 Basic Structures of VHDL

2.1.1 Entities and Architectures

2.1.2 Entity-Architecture Outline

2.1.3 Entity Ports

2.1.4 Signals and Variables

2.1.5 Logic Value System

2.1.6 Resolutions

2.2 Combinational Circuits

2.2.1 Gate Level Combinational Circuits

2.2.2 Gate Level Synthesis

2.2.3 Descriptions by Use of Equations

2.2.4 Instantiating Other Modules

2.2.5 Synthesis of Assignment Statements

2.2.6 Descriptions with Sequential Flow

2.2.7 Combinational Rules

2.2.8 Bussing

2.2.9 Synthesizing Procedural Blocks

2.3 Sequential Circuits

2.3.1 Basic Memory Elements at the Gate Level

2.3.2 Memory Elements Using Procedural Statements

2.3.3 Flip-flop Synthesis

2.3.4 Registers, Shifters and Counters

2.3.5 Synthesis of Shifters and Counters

2.3.6 State Machine Coding

2.3.7 State Machine Synthesis

2.3.8 Memories

2.4 Writing Testbenches

2.5 Synthesis Issues

2.6 VHDL Essential Terminologies

2.6.1 Design

2.6.2 Analysis

2.6.3 Library

2.6.4 Standard Packages

2.6.5 Elaboration

2.6.6 Event Driven Simulation

2.6.7 Concurrency

2.6.8 Concurrent Bodies

2.6.9 Sequentiality

2.6.10 Sequential Bodies

2.6.11 VHDL Objects and Classes

2.6.12 Real Time

2.6.13 Delta Delay

2.6.14 Scheduling

2.6.15 Resolution

2.6.16 Code Formal

2.7 Summary

Problems

Suggested Reading

Chapter 3 VHDL Constructs for Structure and Hierarchy Descriptions

3.1 Basic Components

3.1.1 Basic Model

3.2 Component Instantiations

3.2.1 Direct Instantiation

3.2.2 Component Instantiation

3.3 Iterative Networks

3.3.1 Multi-bit Vectors

3.3.2 Multi-instance Generations

3.3.3 Simplified Generations

3.4 Binding Alternatives

3.5 Association Methods

3.6 Generic Parameters

3.6.1 Using Generic Default Values

3.6.2 Generic Map Aspect

3.6.3 Generic Association List

3.7 Design Configuration

3.7.1 Basic Configuration Declaration

3.7.2 Incremental Configuration

3.7.3 Configuring Nested Components

3.7.4 Indexing Block Configurations

3.7.5 Instantiating a Design Unit

3.8 Design Simulation

3.9 Summary

Problems

Suggested Reading

Chapter 4 Concurrent Constructs for RT Level Descriptions

4.1 Concurrent Signal Assignments

4.1.1 Simple Assignments

4.1.2 Conditional Signal Assignment

4.1.3 Selected Signal Assignment

4.2 Guarded Signal Assignments

4.2.1 GUARD Signal and Expression

4.2.2 Block Statement

4.2.3 Block Statement Ports

4.2.4 Nested Block Statements

4.2.5 Guarded Signals

4.2.6 Timing Disconnections

4.3 Summary

Problems

Suggested Reading

Chapter 5 Sequential Constructs for RT Level Descriptions

5.1 Process Statement

5.1.1 Declarative Part of a Process

5.1.2 Statement Part of a Process

5.1.3 Process Sensitivity List

5.1.4 Postponed Processes

5.1.5 Passive Processes

5.2 Sequential Wait Statements

5.3 VHDL Subprograms

5.3.1 Function Definition

5.3.2 Procedure Definition

5.3.3 Language Aspects of Subprograms

5.3.4 Nesting Subprograms

5.4 VHDL Library Structure

5.4.1 Creating Libraries

5.4.2 Using Libraries

5.5 Packaging Utilities and Components

5.5.1 A Package of Utilities

5.5.2 A Package of Components

5.6 Sequential Statements

5.6.1 If Statement

5.6.2 Loop Statement

5.6.3 Case Statement

5.6.4 Assertion Statement

5.7 Summary

Problems

Suggested Reading

Chapter 6 VHDL Language Utilities and Packages

6.1 Type Declarations and Usage

6.1.1 Enumeration Type for Multi-Value Logic

6.1.2 Using Real Numbers

6.1.3 Type Conversions

6.1.4 Physical Types

6.1.5 Array Declarations

6.1.6 File Type and External File I/O

6.2 VHDL Operators

6.2.1 Logical Operators

6.2.2 Relational Operators

6.2.3 Shift Operators

6.2.4 Adding Operators

6.2.5 Sign Operators

6.2.6 Multiplying Operators

6.2.7 Other Operators

6.2.8 Aggregate Operation

6.3 Operator and Subprogram Overloading

6.3.1 Operator Overloading

6.3.2 Subprogram Overloading

6.4 Other Types and Type-Related Issues

6.4.1 Subtypes

6.4.2 Record Types

6.4.3 Alias Declaration

6.4.4 Access Types

6.4.5 Global Objects

6.4.6 Type Conversions

6.4.7 Standard Nine-Value Logic

6.5 Predefined Attributes

6.5.1 Array Attributes

6.5.2 Type Attributes

6.5.3 Signal Attributes

6.5.4 Entity Attributes

6.5.5 User-Defined Attributes

6.6 Standard Libraries and Packages

6.6.1 STANDARD Package

6.6.2 TEXTIO Package and ASCII I/O

6.6.3 Std_logic_1164 Package

6.6.4 Std_logic_arith Package

6.7 Summary

Problems

Suggested Reading

Chapter 7 VHDL Signal Model

7.1 Characterizing Hardware Languages

7.1.1 Timing and Concurrency of Operations

7.2 Signal Assignments

7.2.1 Inertial Delay Mechanism

7.2.2 Transport Delay Mechanism

7.2.3 Comparing Inertial and Transport

7.3 Concurrent and Sequential Assignments

7.3.1 Concurrent Assignments

7.3.2 Events and Transactions

7.3.3 Delta Delay

7.3.4 Sequential Placement of Transactions

7.4 Multiple Concurrent Drivers

7.4.1 Resolving between Multiple Driving Values

7.4.2 Resolutions with Guarded Assignments

7.4.3 Resolving INOUT Signals

7.4.4 Standard Resolution

7.5 Summary

Problems

Suggested Reading

Chapter 8 Hardware Cores and Models

8.1 Synthesis Rules and Styles

8.1.1 Combinational Cores

8.1.2 Sequential Cores

8.1.3 Finite State Machines

8.2 Memory and Queue Structures

8.2.1 Generic RAM Core

8.2.2 Synthesizable Push-Pop Stack

8.2.3 Synthesizable Circular FIFO

8.2.4 Dynamic Access Type FIFO

8.3 Arithmetic Cores

8.3.1 Array Multiplier

8.3.2 Carry-Lookahead Adder

8.3.3 Synthesizable Booth Multiplier

8.4 Components with Separate Control and Data Parts

8.4.1 Sequential Multiplier

8.4.2 von Neumann Computer Model

8.5 Summary

Problems

Suggested Reading

Chapter 9 Core Design Test and Testability

9.1 Issues Related to Design Test

9.1.1 Design Test

9.1.2 Testbench

9.1.3 Coverage

9.2 Simple Testbenches

9.2.1 Combinational Circuit Testing

9.2.2 Sequential Circuit Testing

9.3 Testbench Techniques

9.3.1 Arbitrary Test Data

9.3.2 Random Test Data

9.3.3 Applying Synchronized Data

9.3.4 Synchronized Display of Results

9.3.5 Displaying Interval Objects

9.3.6 An Interactive Testbench

9.3.7 Queued Data Application

9.3.8 Text File Stimuli and Response

9.4 Complete System Testing

9.4.1 Multiplier Testing

9.4.2 Processor Testing

9.5 Issues Related to Manufacturing Test

9.5.1 Manufacturing Test

9.5.2 Fault Model

9.5.3 Test Generation

9.5.4 Fault Simulation

9.5.5 Fault Coverage

9.5.6 Testability

9.6 Core Test Support Modules

9.6.1 LFSR

9.6.2 MISR

9.7 Scan Design and Test Application

9.7.1 Starting Design

9.7.2 Scan Insertion

9.7.3 Scan Testbench

9.7.4 Top Level Tester

9.8 Memory BIST

9.8.1 Memory BIST Architecture

9.8.2 Test Session

9.8.3 BIST Controller

9.8.4 BIST Structure

9.8.5 BIST Tester

9.9 Summary

Problems

Suggested Reading

Chapter 10 Design, Test and Application of a Processor Core

10.1 Design of SAYEH Processor Core

10.1.1 Details of Processor Functionality

10.1.2 SAYEH Datapath

10.2 SAYEH VHDL Description

10.2.1 Data Components

10.2.2 SAYEH Datapath

10.2.3 SAYEH Controller

10.2.4 Complete SAYEH Processor

10.3 SAYEH Testbench / Assembler / Memory Model

10.3.1 Top Level VHDL Testbench

10.3.2 Memory Model

10.3.3 Assembler

10.3.4 Memory Read

10.3.5 Memory Write

10.3.6 Memory File Handling

10.3.7 Sorting Test Program

10.4 SAYEH as an Embedded Processor Core

10.4.1 Embedded Core Based Design

10.4.2 Filter Design

10.4.3 Core Based Architecture

10.4.4 FIR Program

10.4.5 FIR Memory and IO Maps

10.4.6 Filter Software

10.5 Summary

Problems

Suggested Reading

Appendixes

A: VHDL Keywords

B: VHDL Language Grammar

C: VHDL Standard Packages

C.1 STANDARD Package

C.2 TEXTIO Package

D: STD_LOGIC_1164 Package

E: STD_LOGIC_TEXTIO Package

F: STD_LOGIC_ARITH Package

G: STD_LOGIC_SIGNED

H: STD_LOGIC_UNSIGNED

I: math_real Package

Index