Basics of CMOS Cell Design

Basics of CMOS Cell Design

Authors: Etienne Sicard and Sonia Delmas Bendhia

Published: February 2007

eISBN: 9780071509060 0071509062 | ISBN: 9780071488396

Contents

Preface

Acknowledgments

Abbreviations and Symbols

1. Introduction

1.1 General Trends

1.2 The Device Scale Down

1.3 Frequency Improvements

1.4 Layers

1.5 Density

1.6 Design Trends

1.7 Market

1.8 Conclusion

References

Exercises

2. The MOS Devices and Technology

2.1 Properties of Silicon

2.2 N-type and P-type Silicon

2.3 Silicon Dioxide

2.4 Metal Materials

2.5 The MOS Switch

2.6 The MOS Aspect

2.7 MOS Layout

2.8 Dynamic MOS Behaviour

2.9 The Perfect Switch

2.10 Layout Considerations

2.11 CMOS Process

2.12 Conclusion

References

Exercises

3. The MOS Modelling

3.1 Introduction to Modelling

3.2 MOS Model 1

3.3 MOS Model 3

3.4 The BSIM4 MOS Model

3.5 Specific MOS Devices

3.6 Process Variations

3.7 Concluding Remarks

References

Exercises

4. The Inverter

4.1 Logic Symbol

4.2 CMOS Inverter

4.3 Inverter Layout

4.4 Inverter Simulation

4.5 Power Consumption

4.6 Static Characteristics

4.7 Random Simulation

4.8 The Inverter as a Library Cell

4.9 3-State Inverter

4.10 All nMOS Inverters

4.11 Ring Oscillator

4.12 Latch-up Effect

4.13 Conclusion

References

Exercises

5. Interconnects

5.1 Introduction

5.2 Metal Layers

5.3 Contact and Vias

5.4 Design Rules

5.5 Capacitance Associated with Interconnects

5.6 Resistance Associated with Interconnects

5.7 Signal Transport

5.8 Improved Signal Transport

5.9 Repeaters for Improved Signal Transport

5.10 Crosstalk Effects in Interconnects

5.11 Antenna Effect

5.12 Inductance

5.13 Conclusion

References

Exercises

6. Basic Gates

6.1 Introduction

6.2 Combinational Logic

6.3 CMOS Logic Gate Concept

6.4 The NAND Gate

6.5 The AND Gate

6.6 The NOR Gate

6.7 The OR Gate

6.8 The XOR Gate

6.9 Complex Gates

6.10 Multiplexor

6.11 Shifters

6.12 Description of Basic Gates in Verilog

6.13 Conclusion

References

Exercises

7. Arithmetics

7.1 Data Formats

7.2 The Adder Circuit

7.3 Adder Cell Design

7.4 Ripple-carry Adder

7.5 Signed Adder

7.6 Fast Adder Circuits

7.7 Substractor Circuit

7.8 Comparator Circuit

7.9 Student Project: A Decimal Adder

7.10 Multiplier

7.11 Conclusion

References

Exercises

8. Sequential Cell Design

8.1 The Elementary Latch

8.2 RS Latch

8.3 D Latch

8.4 Edge-trigged D Register

8.5 Clock Divider

8.6 Synchronous Counters

8.7 Shift Registers

8.8 A 24-hour Clock

8.9 Conclusion

References

Exercises

9. Analog Cells

9.1 Resistor

9.2 Capacitor

9.3 The MOS Device for Analog Design

9.4 Diode-connected MOS

9.5 Voltage Reference

9.6 Current Mirror

9.7 The MOS Transconductance

9.8 Single Stage Amplifier

9.9 Simple Differential Amplifier

9.10 Wide Range Amplifier

9.11 On-chip Voltage Regulator

9.12 Noise

9.13 Conclusion

References

Exercises

10. Conclusion

Appendices

A. Design Rules

A.1 Lambda Units

A.2 Layout Design Rules

A.3 Pads

A.4 Electrical Extraction Principles

A.5 Node Capacitance Extraction

A.6 Resistance Extraction

A.7 Simulation Parameters

A.8 Technology Files for Dsch

B. Microwind Program Operation and Commands

B.1 Getting Started

B.2 List of Commands in Microwind

C. Dsch Logic Editor Operation and Commands

C.1 Getting Started

C.2 Commands

D. Quick Reference Sheet

D.1 Microwind Menus

D.2 Microwind Simulation Menu

D.3 Dsch Menus

D.4 List of Files

D.5 List of Measurement Files

Glossary

Index

Software Download Information

Authors’ Profiles