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CITATION

Weng Fook, Lee. VLIW Microprocessor Hardware Design. US: McGraw-Hill Professional, 2007.

VLIW Microprocessor Hardware Design

Authors: Lee Weng Fook

Published:  August 2007

eISBN: 9780071595841 0071595848 | ISBN: 9780071497022
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  • Contents
  • Preface
  • Acknowledgments
  • Trademarks
  • Chapter 1. Introduction
  • 1.1 Types of Microprocessors
  • 1.2 Types of Microprocessor Architecture
  • Chapter 2. Design Methodology
  • 2.1 Technical Specification
  • 2.1.1 Instruction Set of VLIW Microprocessor
  • 2.1.2 Definition of Opcode for VLIW Instruction Set
  • 2.1.3 Definition of VLIW Instruction
  • 2.2 Architectural Specification
  • 2.3 Microarchitecture Specification
  • Chapter 3. RTL Coding, Testbenching, and Simulation
  • 3.1 Coding Rules
  • 3.2 RTL Coding
  • 3.2.1 Module fetch RTL Code
  • 3.2.2 Module decode RTL Code
  • 3.2.3 Module register file RTL Code
  • 3.2.4 Module execute RTL Code
  • 3.2.5 Module writeback RTL Code
  • 3.2.6 Module vliwtop RTL Code
  • 3.3 Testbenches and Simulation
  • 3.3.1 Creating and Using a Testplan
  • 3.3.2 Code Coverage
  • 3.4 Synthesis
  • 3.4.1 Standard Cell Library
  • 3.4.2 Design Constraints
  • 3.4.3 Synthesis Tweaks
  • 3.5 Formal Verification
  • 3.6 Pre-layout Static Timing Analysis
  • 3.7 Layout
  • 3.7.1 Manual/Custom Layout
  • 3.7.2 Semi-custom/Auto Layout
  • 3.7.3 Auto Place and Route
  • 3.8 DRC / LVS
  • 3.9 RC Extraction
  • 3.10 Post-layout Logic Verification
  • 3.11 Post-layout Performance Verification
  • 3.12 Tapeout
  • 3.13 Linking Front End and Back End
  • 3.14 Power Consumption
  • 3.15 ASIC Design Testability
  • Chapter 4. FPGA Implementation
  • 4.1 FPGA Versus ASIC
  • 4.2 FPGA Design Methodology
  • 4.3 Testing FPGA
  • 4.4 Structured ASIC
  • Appendix A. Testbenches and Simulation Results
  • Appendix B. Synthesis Results, Gate Level Netlist
  • Bibliography
  • Index