Embedded Core Design with FPGAs

Embedded Core Design with FPGAs

Authors: Zainalabedin Navabi

Published: 2007

ISBN: 9780071712125 0071484701

Contents

Preface

Introduction

Acknowledgments

CHAPTER

1 Elements of Embedded Design

1.1 Abstraction Levels

1.1.1 Transistors to Programs

1.1.2 Mixed Level Hardware

1.1.3 Design Specification

1.2 Embedded System Design Flow

1.2.1 Hardware/Software Partitioning

1.2.2 Hardware Part

1.2.3 Software Part

1.2.4 Interconnection Specification

1.2.5 Common Hardware/Software Simulation

1.2.6 Hardware Synthesis

1.2.7 Software Compilation

1.2.8 Interconnection Hardware Generation

1.2.9 Design Integrator

1.3 Design Tools

1.3.1 Block Diagram Description

1.3.2 HDL and Other Hardware Simulators

1.3.3 Programming Language Compilers

1.3.4 Netlist Simulator

1.3.5 Instruction Set Simulator

1.3.6 Hardware Synthesis Tool

1.3.7 Compiler for Machine Language Generation

1.3.8 Software Builder and Debugger

1.3.9 Embedded System Integrator

1.4 New Hardware Design Trends

1.4.1 Configurable Processors

1.4.2 Standard Bus Structure

1.4.3 Software Programming

1.4.4 Software Utilities

1.5 Summary

2 Logic Design Concepts

2.1 Number Systems

2.1.1 Binary Numbers

2.1.2 Hexadecimal Numbers

2.2 Binary Arithmetic

2.2.1 Signed Numbers

2.2.2 Binary Addition

2.2.3 Binary Subtraction

2.2.4 Two’s Complement System

2.2.5 Overflow

2.2.6 Fixed Point Numbers

2.2.7 Floating Point Numbers

2.3 Basic Logic Gates and Structures

2.3.1 Logic Value System

2.3.2 Logic Function Representation

2.3.3 Transistors

2.3.4 CMOS Inverter

2.3.5 CMOS NAND

2.3.6 CMOS NOR

2.3.7 AND and OR gates

2.3.8 XOR gate

2.3.9 MUX gate

2.3.10 Three-State Gates

2.3.11 Look-up Tables (LUT)

2.4 Designing Combinational Circuits

2.4.1 Boolean Algebra

2.4.2 Karnaugh Maps

2.4.3 Don’t Care Values

2.4.4 Minimal Coverage

2.4.5 Iterative Hardware

2.4.6 Multiplexers and Decoders

2.4.7 Activity Levels

2.4.8 Enable / Disable Inputs

2.4.9 A High-Level Design

2.5 Storage Elements

2.5.1 The Basic Latch

2.5.2 Clocked D Latch

2.5.3 Flip-Flops

2.5.4 Flip-Flop Control

2.5.5 Registers

2.6 Sequential Circuit Design

2.6.1 Finite State Machines

2.6.2 Designing State Machines

2.6.3 Mealy and Moore Machines

2.6.4 One-Hot Realization

2.6.5 Sequential Packages

2.7 Memories

2.7.1 Static RAM Structure

2.8 Bidirectional IO

2.9 A Comprehensive Example: Serial Adder

2.9.1 Problem Statement

2.9.2 Design Partitioning

2.9.3 Datapath Design

2.10 Summary

3 RTL Design with Verilog

3.1 Basic Structures of Verilog

3.1.1 Modules

3.1.2 Module Outline

3.1.3 Module Ports

3.1.4 Module Variables

3.1.5 Logic Value System

3.1.6 Wire (net) Resolutions

3.2 Combinational Circuits

3.2.1 Gate Level Combinational Circuits

3.2.2 Gate Level Synthesis

3.2.3 Descriptions by Use of Equations

3.2.4 Instantiating Other Modules

3.2.5 Synthesis of Assignment Statements

3.2.6 Descriptions with Procedural Statements

3.2.7 Combinational Rules

3.2.8 Synthesizing Procedural Blocks

3.2.9 Bussing

3.3 Sequential Circuits

3.3.1 Basic Memory Elements at the Gate Level

3.3.2 Memory Elements Using Procedural Statements

3.3.3 Flip-flop Synthesis

3.3.4 Registers, Shifters and Counters

3.3.5 Synthesis of Shifters and Counters

3.3.6 State Machine Coding

3.3.7 State Machine Synthesis

3.3.8 Memories

3.4 Writing Testbenches

3.4.1 Generating Periodic Data

3.4.2 Random Input Data

3.4.3 Timed Data

3.5 Sequential Multiplier Specification

3.5.1 Shift-and-Add Multiplication Process

3.5.2 Sequential Multiplier Design

3.5.3 Multiplier Testing

3.6 Synthesis Issues

3.7 Summary

4 Computer Hardware and Software

4.1 Computer System

4.2 Computer Software

4.2.1 Machine Language

4.2.2 Assembly Language

4.2.3 High-Level Language

4.2.4 C Programming Language

4.3 Instruction Set Architecture

4.4 SMPL-CPU Design

4.4.1 CPU Specification

4.4.2 Single-Cycle Implementation

4.4.3 Multi-Cycle Implementation

4.5 SAYEH Design and Test

4.5.1 Details of Processor Functionality

4.5.2 SAYEH Datapath

4.5.3 SAYEH Verilog Description

4.5.4 SAYEH Top-Level Testbench / Assembler

4.5.5 SAYEH Hardware Realization

4.6 Summary

5 Field Programmable Devices

5.1 Read Only Memories

5.1.1 Basic ROM Structure

5.1.2 NOR Implementation

5.1.3 Distributed Gates

5.1.4 Array Programmability

5.1.5 Memory View

5.1.6 ROM Variations

5.2 Programmable Logic Arrays

5.2.1 PAL Logic Structure

5.2.2 Product Term Expansion

5.2.3 Three-State Outputs

5.2.4 Registered Outputs

5.2.5 Commercial Parts

5.3 Complex Programmable Logic Devices

5.3.1 Altera’s MAX 7000S CPLD

5.4 Field Programmable Gate Arrays

5.4.1 Altera’s FLEX 10K FPGA

5.4.2 Altera’s Cyclone FPGA

5.5 Summary

6 Tools for Design and Prototyping

6.1 Hardware Design Flow

6.1.1 Datapath of Serial Adder

6.1.2 Serial Adder Controller

6.2 HDL Simulation and Synthesis

6.2.1 Pre-Synthesis Simulation

6.2.2 Module Synthesis

6.2.3 Post-Synthesis Simulation

6.3 Mixed-Level Design with Quartus II

6.3.1 Project Specification

6.3.2 Block Diagram Design File

6.3.3 Creating and Inserting Design Components

6.3.4 Wiring Design Components

6.3.5 Design Compilation

6.3.6 Design Simulation

6.3.7 Synthesis Results

6.4 Design Prototyping

6.4.1 UP3 Board Specification

6.4.2 DE2 Board Specification

6.4.3 Programming DE2 Cyclone II

6.5 Summary

7 Design of Utility Hardware Cores

7.1 Library Management

7.2 Basic IO Device Handling

7.2.1 Debouncer

7.2.2 Single Stepper

7.2.3 Utilizing UP3 Basic IO

7.2.4 Utilizing DE2 Basic IO

7.3 Frequency Dividers

7.4 Seven Segment Displays

7.4.1 SSD Driver

7.4.2 Testing DE2 SSD Driver

7.5 LCD Display Adaptor

7.5.1 Writing into LCD

7.5.2 LCD Initialization

7.5.3 Display Driver with Initialization

7.5.4 Testing the LCD Driver (UP3)

7.5.5 Testing the LCD Driver (DE2)

7.6 Keyboard Interface Logic

7.6.1 Serial Data Communication

7.6.2 Power-On Routine

7.6.3 Codes and Commands

7.6.4 Keyboard Interface Design

7.7 VGA Interface Logic

7.7.1 VGA Driver Operation

7.7.2 Monitor Synchronization Hardware

7.7.3 Character Display

7.7.4 VGA Driver for Text Data

7.7.5 VGA Driver Prototyping (UP3)

7.7.6 VGA Driver Prototyping (DE2)

7.8 Summary

8 Design with Embedded Processors

8.1 Embedded Design Steps

8.1.1 Processor Selection

8.1.2 Processor Interfacing

8.1.3 Developing Software

8.2 Filter Design

8.2.1 Filter Concepts

8.2.2 FIR Filter Hardware Implementation

8.2.3 FIR Embedded Implementation

8.2.4 Building the FIR Filter

8.3 Design of a Microcontroller

8.3.1 System Platform

8.3.2 Microcontroller Architecture

8.4 Summary

9 Design of an Embedded System

9.1 Designing an Embedded System

9.2 Nios II Processor

9.2.1 Configurability Features of Nios II

9.2.2 Processor Architecture

9.2.3 Instruction Set

9.2.4 Nios II Alternative Cores

9.3 Avalon Switch Fabric

9.3.1 Avalon Specification

9.3.2 Address Decoding Logic

9.3.3 Data-path Multiplexing

9.3.4 Wait-state Insertion

9.3.5 Pipelining

9.3.6 Endian Conversion

9.3.7 Native Address Alignment and Dynamic Bus Sizing

9.3.8 Arbitration for Multi-Master Systems

9.3.9 Burst Management

9.3.10 Clock Domain Crossing

9.3.11 Interrupt Controller

9.3.12 Reset Distribution

9.4 SOPC Builder Overview

9.4.1 Architecture of SOPC Builder Systems

9.4.2 Functions of SOPC Builder

9.5 IDE Integrated Development Environment

9.5.1 IDE Project Manager

9.5.2 Source Code Editor

9.5.3 C/C++ Compiler

9.5.4 Debugger

9.5.5 Flash Programmer

9.6 An Embedded System Design: Calculator

9.6.1 System Specification

9.6.2 Calculating Engine

9.6.3 Calculator IO Interface

9.6.4 Design of Calculating Engine

9.6.5 Building Calculator Software

9.6.6 Calculator Program

9.6.7 Completing the Calculator System

9.7 Summary

APPENDIX

A Nios II Instruction Set

A.1 Data Transfer Instructions

A.2 Arithmetic and Logical Instructions

A.3 Move Instructions

A.4 Comparison Instructions

A.5 Shift and Rotate Instructions

A.6 Program Control Instructions

A.7 Other Control Instructions

A.8 Custom Instructions

A.9 No-Op Instruction

A.10 Potential Unimplemented Instructions

B Additional Resources

Index