3D IC Stacking Technology

3D IC Stacking Technology

Authors: Banqiu Wu, Ajay Kumar and Sesh Ramaswami

Published: July 2011

eISBN: 9780071741965 0071741968 | ISBN: 9780071741958

Cover

Contents

Contributors

Foreword

Preface

Chapter 1: Introduction to High-Density Through Silicon Stacking Technology

1.1: Background

1.2: 3D Integrated Circuit Technologies

1.2.1: 3D IC Types

1.2.2 : Via-Middle Through Silicon Stacking

1.3 : TSS Drivers and Product Architectures

1.3.1 : Overall Drivers

1.3.2 : Examples of Architectural Uniqueness from Through Silicon Stacking

1.3.3 : Software Simplification Enabled by TSS

1.4 : Markets for TSS

1.5 : TSS Supply Chain Options

1.6 : Challenges for Through Silicon Stacking

1.6.1 : Manufacturing Cost

1.6.2 : Design Tools, Flow, Kits

1.6.3 : Design for Test and ManufacturingTest

1.6.4 : Thermal Hotspots, Mechanical Stress, and Power Delivery

1.6.5 : Fabrication Processes, Materials, and Structures

1.6.6 : Technology Adoption

1.7 : Concluding Remarks

References

Chapter 2: A Practical Design Eco-System for Heterogeneous 3D IC Products

2.1 : Requirements for 3D Design Eco-System

2.1.1 : 2D Design Experiences

2.1.2 : Causes for Incremental Design Specification Instability in 3D

2.1.3 : Causes for Incremental Process Constraint Instability in 3D

2.1.4 : 3D Design Eco-System

2.2 : PathFinding

2.2.1 : Path Finding Objectives

2.2.2 : Ideal Path Finding Flow

2.2.3 : Path Finding versus Design-Authoring Requirements

2.2.4 : 3D Path Finding and Trade-Off Discussion

2.3 : TechTuning

2.3.1 : TechTuning Objectives

2.3.2 : TechTuning Implementation

2.3.3 : TechTuning Infrastructure

2.4 : Design Authoring

2.4.1 : Design Enablement

2.4.2 : Synthesis and Simulation

2.4.3 : Physical Design, Extraction, and Verification

2.4.4 : Utility Insertion

2.4.5 :Timing and Power Analyses

2.5 : Summary and Conclusions

References

Chapter 3: Design Automation and TCAD Tool Solutions for Through Silicon Via–Based 3D IC Stack

3.1 : Introduction

3.2 : Planning: 3D System Architecture

3.2.1 : PathFinding

3.2.2 : Gross Thermal Analysis

3.2.3 : Board-Package-IC Co-Design

3.3 : Implementation

3.3.1 : Partitioning

3.3.2 : Floor Planning and Place and Route

3.3.3 : Clock and Power Networks

3.3.4 : Testability

3.3.5 : Visualization

3.4 : Verification and Sign-Off

3.4.1 : Extraction

3.4.2 : Power-Rail Analysis

3.5 : Modeling Thermomechanical-Stress-RelatedIssues in TSV

3.5.1 : New Thermomechanical Stress in a 3D TSV Stack

3.5.2 : TSV Stress-Induced Performance Modulation

3.5.3 : TSV Stress-Induced Reliability Concerns

3.5.4 : TSV Diameter Effects

3.5.5 : Insulation Material Effects

3.5.6 : TSV Material Effects

3.6 : Summary and Conclusions

References

Chapter 4: Process Integration for TSV Manufacturing

4.1 : Introduction

4.2 : Evolutionary Path to 3D Stacking

4.2.1 : Die Stacking

4.2.2 : Stacked Packages

4.2.3 : Micro-Bumps, Pillar and Re-Distribution Layers

4.2.4 : Interposers

4.2.5 : 3D IC with TSV

4.3 : Stacking Methods

4.4 : TSV Process Overview

4.4.1 : TSV-Related Processing on Full-Thickness Wafers

4.4.2 : TSV-Related Processing on Thinned Wafers

4.5 : TSV Unit Processes

4.5.1 : Lithography

4.5.2 : TSV Etch, Photoresist Strip, and Wet Clean

4.5.3 : Insulator Deposition with Chemical Vapor Deposition

4.5.4 : Metal Barrier/Seed

4.5.5 : Via Fill

4.5.6 : Chemical Mechanical Polish (CMP) of Copper

4.5.7 : Wafer Bonding

4.5.8 : Wafer Thinning for TSV Processes

4.5.9 Metrology and Inspection

4.6 : TSV-Integrated Processing

4.6.1 : Via-First TSVs

4.6.2 : Via-Middle TSVs

4.6.3 : Vias from the Topside

4.6.4 : Via-Last TSVs

4.6.5 : Via Reveal Process (Revealing the Via-Middle TSVs from the Backside)

4.6.6 : Summary

References

Chapter 5: High-Aspect-Ratio Silicon Etch for TSV

5.1 : Introduction

5.1.1 : History of High-Aspect-Ratio (HAR) Silicon Etch

5.1.2 : HAR Silicon-Etch Applications

5.1.3 : HAR Silicon-Etch Methods

5.2 : Plasma-Etch Fundamentals

5.2.1 : Plasma Principles

5.2.2 : Plasma Sheath

5.2.3 : Mass-Transport Phenomena in Plasmas and TSV Etch

5.2.4 : Chemical Reactions and Kinetics

5.2.5 Plasma Sources

5.2.6 : Plasma Diagnosis

5.3 : Time-Multiplexed Alternating Process

5.3.1 : Etch Rate and Selectivity

5.3.2 : Profile and Surface Roughness

5.3.3 : Aspect-Ratio-Dependent Etch (ARDE)

5.3.4 : Loading Effects

5.3.5 : Micrograss

5.3.6 : Notching

5.4 : Steady-State Etch Process

5.4.1 : Reactive Ion Etch (RIE)

5.4.2 : Etching at Cryogenic Condition

5.4.3 : Simultaneous Etch with Passivation

5.5 : Etch Method and Equipment

5.5.1 : RIE and Early Etchers

5.5.2 : Etchers Using Magnetic Field

5.5.3 : Inductively Coupled Plasma Etchers

5.6 : Summary

References

Chapter 6: Dielectric Deposition for Through Silicon Vias

6.1 : Introduction to Dielectric Films

6.2 : Key Requirements for Dielectric Process Used in 3D TSV

6.2.1 : Deposition Temperature

6.2.2 : Confomality of Dielectrics

6.2.3 : Hermeticity

6.2.4 : Electric Properties of Dielectrics

6.2.5 : Adhesion

6.3 : Fundamentals of Chemical Vapor Deposition (CVD)

6.4 : CVD Methods for TSV Application

6.4.1 : Atmospheric Pressure Chemical Vapor Deposition (APCVD)

6.4.2 : Low-Pressure CVD (LPCVD)

6.4.3 : Subatmospheric Chemical Vapor Deposition (SACVD)

6.4.4 : Plasma-Enhanced Chemical Vapor Deposition (PECVD)

6.5 : Summary

References

Chapter 7: Barrier and Seed Deposition

7.1 Introduction

7.2 Material Choices

7.3 Deposition Technologies

7.3.1 Introduction

7.3.2 Degas

7.3.3 Pre-Clean

7.3.4 CVD

7.3.5 ALD

7.3.6 PVD

7.4 PVD Technology Details

7.4.1 Introduction

7.4.2 Ionized Metal Sources and Step Coverage

7.5 TSV Application

7.6 Conclusions

Acknowledgments

References

Chapter 8: Copper Electrodeposition for TSV

8.1 Introduction to Plating

8.1.1 General Aspects

8.1.2 Fundamentals

8.1.3 History

8.2 3D Chip Stacking Using Through Silicon Via

8.2.1 General Overview of 3D Chip Stacking

8.2.2 Plating Needs for 3D Chip Stacking

8.2.3 Through Silicon Via Formation

8.3 Copper Plating for TSV

8.3.1 Advantages of Electrodeposition Processes

8.3.2 Applications of Cu Plating for TSV

8.3.3 Via-Processing Steps

8.3.4 Success Criteria

8.3.5 Key Factors

8.3.6 Plating Chemistries

8.3.7 Growth Mechanism

8.3.8 TSV-Integration Challenges

8.3.9 Equipment for Plating

8.4 Summary

Acknowledgments

References

Chapter 9: Chemical Mechanical Polishing for TSV Applications

9.1 Introduction to CMP

9.2 CMP Fundamentals

9.2.1 Removal Rate and Film Properties

9.2.2 Removal Profile Control with Hardware

9.2.3 Planarization Efficiency

9.2.4 Dishing, Erosion, and Corrosion versus Process Conditions

9.2.5 Post-CMP Cleaning

9.2.6 CMP Evolution and Disruptive Technologies

9.3 Process Requirement for TSV versus Cu Damascene

9.4 CMP Process Control and Metrology

9.5 CMP Process for Different TSV-Integration Flows

9.5.1 Cu CMP for Via-Middle

9.5.2 CMP Process for Via-Last

9.5.3 CMP Process Result for TSV

9.6 Wafer Handling and Wafer-Backside Polishing for Via Reveal

9.6.1 Handling of Bonded TSV Wafers

9.6.2 Direct CMP of Si/Cu After Si Grinding

9.6.3 CMP of Dielectric and Cu Nails After Passivation

9.7 Further CMP-Process Variables and Characterization

9.7.1 Local Pattern-Density Effect

9.7.2 Effect of Cu-Plating Chemistry and Annealing on Cu-CMP Rates

9.7.3 CMP Dishing Response to Different Barrier Metals

9.7.4 Electrical Characterization Post CMP

9.8 Post-CMP Defect Inspection

9.8.1 In-Film Defects Between Cu Seed and ECD Cu

9.8.2 Voids in Cu Vias

9.8.3 CMP Residue

9.8.4 Delamination and Arcing Defects

9.9 Conclusions

Acknowledgments

References

Chapter 10: Temporary and Permanent Bonding

10.1 Introduction to Wafer Bonding for TSV Integration

10.2 Wafer-to-Wafer Alignment and Bonding for TSV Integration

10.2.1 Introduction

10.2.2 Wafer-to-Wafer Alignment

10.2.3 Wafer Bonding for TSV Integration

10.3 Comparison of Stacking Schemes: W2W, C2W, and Advanced C2W

10.4 Temporary Bonding and Debonding for Thin-Wafer Handling and Processing

References

Chapter 11: Assembly and Test Aspects of TSV Technology

11.1 Introduction

11.2 Process Integration

11.2.1 TSV Wafer Finishing

11.2.2 Assembly

11.2.3 Test Strategies for Advanced SiP and 3D/TSV Packages

11.3 TSV Logistics and Supply-Chain Issues

11.4 TSV Design Considerations for Wafer-Backside Bumping

11.5 Thermal Performance of TSV Packages

11.6 Reliability Considerations for TSV Packages

11.7 Electrical Performance of TSV Packages

11.8 Summary and Conclusions

References

Index