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CITATION

Iniewski, Krzysztof. CMOS Nanoelectronics: Analog and RF VLSI Circuits. US: McGraw-Hill Professional, 2011.

CMOS Nanoelectronics: Analog and RF VLSI Circuits

Authors: Krzysztof Iniewski

Published:  July 2011

eISBN: 9780071755665 0071755667 | ISBN: 9780071755658
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  • Contents
  • Contributors
  • Preface
  • Part 1 RF Circuits
  • 1 Analog Nanometer CMOS Circuits
  • 1.1 Introduction
  • 1.2 The Influence of Gate Leakage Currents on the Gain in Regulated Cascodes
  • 1.3 An Operational Amplifier for DVB-H Receivers in 65-nm CMOS
  • 1.4 A Current-Mode Filter in 65-nm CMOS Technology
  • 1.5 A Comparator in 65-nm CMOS Technology with Reduced Delay Time for Low-Supply Voltages
  • 1.6 A Double Bulk Mixer for a Direct Conversion Receiver in 65-nm CMOS Technology
  • 1.7 Conclusion
  • Acknowledgments
  • References
  • 2 Design of Transceivers with Passive Mixers
  • 2.1 Introduction
  • 2.2 Passive Mixers in Direct-Conversion Receivers
  • 2.3 Passive Mixers in Direct-Conversion Transmitters
  • 2.4 Conclusion
  • 2.5 Appendix A: Common-mode and Differential-mode Excitations
  • 2.6 Appendix B: Calculating Baseband Currents Excited by ac Voltages in the Baseband
  • References
  • 3 Design of Portable High-Efficiency Polar Transmitters for Broadband Wireless Applications Using the Envelope-Tracking Technique
  • 3.1 Introduction
  • 3.2 Review of Some State-of-the-Art Polar Transmitters in the Literature
  • 3.3 System Design Considerations of an RF Polar Transmitter Using ET/EER
  • 3.4 Design of Envelope Amplifiers for ET-Based Polar Transmitters
  • 3.5 Design of Monolithic Saturated PA for ET-Based Polar Transmitters
  • 3.6 Measured and Simulated System Results for ET-Based Polar Transmitters
  • 3.7 Conclusions
  • Acknowledgment
  • References
  • 4 All-Digital RF Signal Generation Antoine Frapp´e, Axel Flament, Bruno Stefanelli, Andreas Kaiser and Andreia Cathelin
  • 4.1 Introduction: From Analog RF to Digital RF Transmitters
  • 4.2 Cartesian Transmitter Architectures
  • 4.3 High-Speed Single-Bit Δ Σ Modulator Design for Digital Transmitters
  • 4.4 Single-Bit Output Switching Stages
  • 4.5 Out-of-Band Filtering
  • 4.6 Summary and Prospects
  • Acknowledgments
  • References
  • 5 Frequency Multiplier Design: Techniques and Applications
  • 5.1 Introduction
  • 5.2 Multipliers for Very High-Speed Computing and Communications Systems
  • 5.3 Noise Concepts in Frequency Multipliers
  • 5.4 Single-Transistor Frequency Multipliers
  • 5.5 Mixers with Internal LO Frequency Multiplication
  • 5.6 Odd-Order Frequency Multipliers
  • 5.7 Conclusion
  • References
  • 6 Tunable CMOS RF Filters
  • 6.1 Introduction
  • 6.2 Q-Enhanced Resonators
  • 6.3 Wide-Bandwidth RF Filters
  • 6.4 Automatic Tuning
  • 6.5 Applications
  • 6.6 Summary
  • References
  • 7 Power Mixer for CMOS Power Amplifier
  • 7.1 Introduction
  • 7.2 Considerations for PA Design
  • 7.3 Power Mixer
  • 7.4 A Design Example
  • 7.5 Summary
  • References
  • 8 GaAs HBT Linear Power Amplifier Design for Wireless Communications
  • 8.1 Introduction
  • 8.2 Linear Power Amplifier Design
  • 8.3 Recent Power Amplifier Technologies
  • 8.4 Summary
  • References
  • Part 2 High-Speed Circuits
  • 9 High-Speed Serial I/O Design for Channel-Limited and Power-Constrained Systems
  • 9.1 Introduction
  • 9.2 High-Speed Link Overview
  • 9.3 Channel-Limited Design Techniques
  • 9.4 Low-Power Design Techniques
  • 9.5 Optical Interconnects
  • 9.6 Conclusion
  • References
  • 10 CDMA-Based Crosstalk Cancellation Technique for High-Speed Chip-to-Chip Communication
  • 10.1 Introduction
  • 10.2 Electrical Signaling in High-Speed I/O Links
  • 10.3 CDMA-Based Crosstalk Cancellation
  • 10.4 Equalization and Clocking
  • 10.5 CDMA-Based Four-Wire Signaling Transceivers
  • 10.6 Conclusion
  • References
  • 11 Equalization Techniques for High-Speed Serial Data Links
  • 11.1 Basics of High-Speed Serial Data Links
  • 11.2 Channel Equalization
  • 11.3 Equalizer Tuning Schemes
  • 11.4 Conclusion
  • Acknowledgments
  • References
  • 12 Δ Σ Fractional-N Phase-Locked Loop
  • 12.1 Overview
  • 12.2 Hybrid FIR Noise-Filtering Method
  • 12.3 Hardware Demonstrations
  • 12.4 Summary
  • References
  • 13 Design and Applications of Delay-Locked Loops
  • 13.1 Introduction
  • 13.2 DLL Basics (PLL vs. DLL)
  • 13.3 DLL Loop Dynamics
  • 13.4 DLL Applications
  • References
  • 14 Digital Clock Generators Used for Nanometer Processors and Memories
  • 14.1 Introduction
  • 14.2 The Digital Clock Generator
  • 14.3 The Design Methodology for the Clock Generator Used in High-Performance Processors
  • 14.4 The Design Methodology of Clock Generators for High-Speed DRAM Applications
  • 14.5 Conclusions
  • References
  • Part 3 High-Precision Circuits
  • 15 Gain Enhancement and Low-Voltage Techniques for Analog Circuits in Deep Submicrometer CMOS Technologies
  • 15.1 Introduction
  • 15.2 Basic Gain-Enhancement Techniques
  • 15.3 Comparison of Conventional Op-Amps in Fine-Line Technologies
  • 15.4 Schemes for Op-Amp’s Gain Boosting in Fine-Line Technologies
  • 15.5 Gain Boosting Using Partial Positive Feedback and Super Voltage Followers
  • 15.6 Low-Voltage Techniques
  • 15.7 Conclusions
  • References
  • 16 Complementary Switched MOSFET Architecture for Low-Frequency Noise Reduction in Linear Analog CMOS ICs
  • 16.1 Introduction
  • 16.2 Principle: Complementary Switched MOSFET Architecture
  • 16.3 Implementation to Linear Analog CMOS ICs
  • 16.4 Experimental Verification
  • 16.5 Conclusions
  • References
  • 17 Broadband High-Resolution 200 MHz Bandpass Sigma–Delta Modulator with a Software-Based Calibration Scheme
  • 17.1 Introduction
  • 17.2 Bandpass Sigma–Delta Architecture
  • 17.3 Software-Based Calibration Scheme
  • 17.4 Experimental Results
  • 17.5 Conclusions
  • Acknowledgments
  • References
  • 18 Analog-to-Digital Conversion Specifications for Power Line Communication Systems
  • 18.1 Background
  • 18.2 OFDM Modulation in PLC Environments
  • 18.3 Popular ADC Architectures
  • 18.4 ADC Architectures Based on Integer Division
  • 18.5 Conclusion
  • Acknowledgment
  • References
  • 19 Digital-to-Analog Converters for LCDs
  • 19.1 Introduction
  • 19.2 Resistive-String DACs
  • 19.3 Resistor–Capacitor DACs
  • 19.4 Piecewise Linear DACs
  • 19.5 Area-Efficient R-DAC with Polarity Inverter
  • 19.6 Conclusions
  • References
  • 20 Sub-1-V CMOS Bandgap Reference Design Techniques: An Overview
  • 20.1 Introduction
  • 20.2 Design Challenges of Sub-1-V CMOS Bandgap References
  • 20.3 Design of Sub-1-V CMOS Bandgap Voltage References
  • 20.4 Summary
  • Acknowledgments
  • References
  • Index