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CITATION

Perry, Douglas and Foster, Harry. Applied Formal Verification. US: McGraw-Hill Professional, 2005.

Applied Formal Verification

Authors: Douglas Perry and Harry Foster

Published:  April 2005

eISBN: 9780071588898 0071588892 | ISBN: 9780071443722
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  • Contents
  • Preface
  • Chapter 1 Introduction to Verification
  • 1.1 Verification
  • 1.2 Market Window
  • 1.3 Summary
  • Chapter 2 Verification Process
  • 2.1 Verification Plan
  • 2.2 Debug Cycle
  • 2.3 Simulation
  • 2.4 Output Data
  • 2.5 Testbench Development
  • 2.6 Summary
  • Chapter 3 Current Verification Techniques
  • 3.1 HDL Software Simulators
  • 3.2 Accelerated Simulation
  • 3.2.1 Increasing Simulation Speed
  • 3.2.2 Testbench
  • 3.3 Process-Based Accelerator Techniques
  • 3.4 Hardware Emulation
  • 3.5 FPGA Prototyping
  • 3.6 Summary
  • Chapter 4 Introduction to Formal Techniques
  • 4.1 Formal Verification Concepts
  • 4.1.1 What Is Formal Verification?
  • 4.1.2 Formal Boolean Verification
  • 4.1.3 Formal Sequential Verification
  • 4.2 Summary
  • Chapter 5 Formal Basics and Definitions
  • 5.1 Formal Basics
  • 5.1.1 Boolean Satisfiability
  • 5.2 Reachability Analysis
  • 5.3 Definitions
  • 5.4 Summary
  • Chapter 6 Property Specification
  • 6.1 Reasoning about Correct Behavior
  • 6.2 Elements of Property Languages
  • 6.2.1 Linear-Time Temporal Logic
  • 6.2.2 Extended Regular Expressions
  • 6.2.3 High-Level Requirements Modeling
  • 6.3 Property Language Layers
  • 6.3.1 Boolean Layer
  • 6.3.2 Temporal Layer
  • 6.3.3 Verification Layer
  • 6.3.4 Modeling Layer
  • 6.3.5 Events
  • 6.4 Property Classification
  • 6.4.1 Safety versus Liveness
  • 6.4.2 Constraint versus Assertion
  • 6.4.3 Declarative versus Procedural
  • 6.5 PSL Basics
  • 6.5.1 PSL always and never Properties
  • 6.5.2 PSL next Properties
  • 6.5.3 PSL eventually Properties
  • 6.5.4 PSL until Properties
  • 6.5.5 PSL before Properties
  • 6.5.6 PSL Sequences
  • 6.5.7 PSL Built-in Functions
  • 6.5.8 PSL Verification Layer
  • 6.6 SystemVerilog Assertion Basics
  • 6.6.1 SVA Immediate Assertions
  • 6.6.2 SVA Concurrent Assertions
  • 6.6.3 SVA System Functions
  • 6.7 Fair Arbiter Example
  • 6.8 Summary
  • Chapter 7 The Formal Test Plan Process
  • 7.1 Developing a Formal Test Plan
  • 7.2 Rules for Writing a Requirements Model
  • 7.3 AMBA AHB Example
  • 7.3.1 Determine Target Verification
  • 7.3.2 Describe Behavior
  • 7.3.3 Define Formal Specification Interface
  • 7.3.4 Create Requirements Checklist
  • 7.3.5 Formalize Requirements Checklist
  • 7.3.6 Document Verification Strategy
  • 7.3.7 Define Coverage Goals
  • 7.4 Summary
  • Chapter 8 Techniques for Proving Properties
  • 8.1 Cone-of-Influence Reduction
  • 8.2 Abstraction Reduction
  • 8.3 Compositional Reasoning
  • 8.3.1 Unconstrained Decomposition
  • 8.3.2 Assume-Guarantee Reasoning
  • 8.4 Symmetry
  • 8.5 Counter Abstraction
  • 8.5.1 Counter Induction
  • 8.5.2 Counter Reduction
  • 8.6 Nondeterminism
  • 8.7 Gradual Exhaustive Formal Verification
  • 8.8 Summary
  • Chapter 9 Final System Simulation
  • 9.1 Test Plan Revisited
  • 9.2 Module Verification
  • 9.3 Full Simulation from a Simulation Flow
  • 9.4 Full Simulation from a Formal Verification Flow
  • 9.5 Summary
  • Appendix A: IEEE 1850 PSL Property Specification Language
  • A.1 Introduction to IEEE 1850 PSL
  • A.2 Operators and Keywords
  • A.3 PSL Boolean Layer
  • A.4 PSL Temporal Layer
  • A.4.1 SERE
  • A.4.2 Sequence
  • A.4.3 Braced SERE
  • A.4.4 SERE Concatenation ( ; )
  • A.4.5 Consecutive Repetition ( [ * ] )
  • A.4.6 Nonconsecutive Repetition ( [ = ] )
  • A.4.7 Goto Repetition ( [ - > ] )
  • A.4.8 Sequence Fusion ( : )
  • A.4.9 Sequence Non-Length-Matching And (&)
  • A.4.10 Sequence Length-Matching And (&&)
  • A.4.11 Sequence Or ( | )
  • A.4.12 The until* Sequence Operators
  • A.4.13 The within Sequence Operator
  • A.4.14 The next* Operators
  • A.4.15 The eventually! Operator
  • A.4.16 The before* Operators
  • A.4.17 The abort Operator
  • A.4.18 The endpoint Declaration
  • A.4.19 Suffix Implication Operators
  • A.4.20 Logical Implication Operator
  • A.4.21 The always Temporal Operator
  • A.4.22 The never Temporal Operator
  • A.5 PSL Properties
  • A.5.1 Property Declaration
  • A.5.2 Named Properties
  • A.5.3 Property Clocking
  • A.5.4 The forall Property Replication
  • A.6 The Verification Layer
  • A.6.1 The assert Directive
  • A.6.2 The assume Directive
  • A.6.3 The cover Directive
  • A.7 The Modeling Layer
  • A.7.1 prev ( )
  • A.7.2 next ( )
  • A.7.3 stable ( )
  • A.7.4 rose ( )
  • A.7.5 fell ( )
  • A.7.6 isunknown ( )
  • A.7.7 countones ( )
  • A.7.8 onehot ( ), onehot0 ( )
  • A.8 BNF
  • A.8.1 Metasyntax
  • A.8.2 Tokens
  • A.8.3 HDL Dependencies
  • A.8.4 Syntax Productions
  • Appendix B: IEEE 1800 SystemVerilog Assertions
  • B.1 Introduction to IEEE 1800 SystemVerilog
  • B.2 SVA Operators and Keywords
  • B.3 Sequence and Property
  • B.3.1 Temporal Delay
  • B.3.2 Consecutive Repetition
  • B.3.3 Goto Repetition
  • B.3.4 Nonconsecutive Repetition
  • B.3.5 Sequence and Property and
  • B.3.6 Sequence Intersection
  • B.3.7 Sequence and Property or
  • B.3.8 Boolean until (throughout)
  • B.3.9 The within Sequence
  • B.3.10 The Method ended
  • B.3.11 The Method matched
  • B.3.12 The first_match
  • B.3.13 Property Implication
  • B.3.14 Conditional Property Selection
  • B.4 Property Declarations
  • B.4.1 Sequence Composition
  • B.5 The assert, assume, and cover Statements
  • B.6 System Functions
  • B.7 System Tasks
  • B.8 BNF
  • B.8.1 Use of Assertions BNF
  • B.8.2 Assertion Statements
  • B.8.3 Property and Sequence Declarations
  • B.8.4 Property Construction
  • B.8.5 Sequence Construction
  • Bibliography
  • Index