High Performance Integrated Circuit Design

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High Performance Integrated Circuit Design

High Performance Integrated Circuit Design

Authors: Emre Salman and Eby Friedman

Published: August 2012

eISBN: 9780071635752 0071635750 | ISBN: 9780071635769

Cover

About the Authors

Title Page

Copyright Page

Contents

Preface

Acknowledgments

Part I: Background

Chapter 1: Introduction

1.1 Brief History

1.1.1 The Transistor

1.1.2 Integrated Circuit

1.2 More Moore and More Than Moore

1.3 Review of IC Design Objectives

1.4 Book Organization

Chapter 2: Technology Scaling

2.1 Device Scaling

2.1.1 MOS Device Operation

2.1.2 Constant Electric Field Scaling

2.1.3 Constant Voltage Scaling

2.1.4 Comparison between Device Scaling Scenarios

2.2 Small Geometry Effects

2.2.1 Threshold Voltage Roll-Off

2.2.2 Drain-Induced Barrier Lowering

2.2.3 Velocity Saturation

2.2.4 Mobility Degradation

2.3 Device Enhancements

2.3.1 Nonuniform Channel Doping

2.3.2 Strain Engineering

2.3.3 Combining High-K and Metal Gate Structures

2.3.4 Multiple Gate Devices

2.4 Interconnect Scaling

2.4.1 Global versus Local Interconnects

2.4.2 Ideal Scaling

2.4.3 More Realistic Scaling Scenarios

2.4.4 Comparison between Interconnect Scaling Scenarios

2.5 Interconnect Enhancements

2.5.1 Ultra-Low-K Dielectric Material

2.5.2 Three-Dimensional Integration

2.5.3 On-Chip Optical Interconnect

2.5.4 Carbon Based On-Chip Interconnect

2.6 Chapter Summary

Part II: Interconnect Networks

Chapter 3: Interconnect Modeling and Extraction

3.1 Interconnect Design Criteria

3.1.1 Latency

3.1.2 Bandwidth

3.1.3 Noise

3.1.4 Power Dissipation

3.1.5 Physical Area

3.2 Interconnect Capacitance

3.2.1 Components of Interconnect Capacitance

3.2.2 Interconnect Capacitance Extraction

3.3 Interconnect Resistance

3.3.1 Copper Resistivity

3.3.2 Interconnect Resistance Extraction

3.4 Interconnect Inductance

3.4.1 Definitions of Inductance

3.4.2 Frequency Dependence of Inductance

3.4.3 When is On-Chip Inductance Important?

3.4.4 Interconnect Inductance Extraction Process

3.5 Chapter Summary

Chapter 4: Signal Propagation Analysis

4.1 Lumped versus Distributed Models

4.1.1 Lumped Model

4.1.2 Distributed Transmission Line Model

4.1.3 Lumped Representation of Distributed Interconnects

4.1.4 Determining the Highest Frequency of Interest

4.1.5 Closed-Form Solutions

4.2 Model Order Reduction

4.2.1 Elmore Delay for RC Lines

4.2.2 Wyatt Approximation

4.2.3 Bounds on Delay: Penfield-Rubinstein Algorithm

4.2.4 Moment Matching

4.2.5 Asymptotic Waveform Evaluation

4.2.6 Calculating the Moments of an RLC Tree

4.2.7 Advantages and Limitations of AWE

4.2.8 Direct Truncation of the Transfer Function (DTT)

4.2.9 Elmore Delay for RLC Lines

4.2.10 Krylov-Subspace Techniques

4.3 Chapter Summary

Chapter 5: Interconnect Coupling Noise

5.1 Active and Passive Device Noise

5.1.1 Thermal Noise

5.1.2 Shot Noise

5.1.3 Flicker Noise

5.2 Capacitive Coupling Noise

5.2.1 Scaling Characteristics of Coupling Capacitance

5.2.2 Dependence of Coupling Capacitance on Switching Activity

5.2.3 Models of Capacitively Coupled Noise

5.3 Inductive Coupling Noise

5.4 Bus Structured Interconnects

5.5 Effects of Coupling Noise

5.5.1 Functional Failure

5.5.2 Glitch Power Consumption

5.5.3 Increased Delay Uncertainty

5.6 Chapter Summary

Chapter 6: Global Signaling

6.1 Interconnect Topology Optimization

6.1.1 Constructing an Interconnect Tree

6.1.2 Wire Sizing, Spacing, and Shaping

6.2 Circuit Level Signaling

6.2.1 Capacitive Load: Tapered Buffer Design

6.2.2 Exponential Tapering Factor

6.2.3 Improvements over Exponential Tapering Factor

6.2.4 Resistive Load: Repeater Insertion in RC Lines

6.2.5 Optimum Number and Size of Repeaters

6.2.6 Inductive Load: Repeater Insertion in RLC Lines

6.2.7 Repeater Insertion in Tree Structured Interconnect

6.2.8 Repeater Insertion to Reduce Coupling Noise

6.2.9 Shield Insertion

6.2.10 Gate Sizing

6.2.11 Signal Rerouting and Wire Reordering

6.3 Tradeoffs in Global Signaling

6.4 Chapter Summary

Part III: Power Management

Chapter 7: Power Generation

7.1 Characteristics of Voltage Regulators

7.1.1 Regulation Efficiency

7.1.2 Energy Efficiency

7.2 Linear Regulators

7.2.1 General Characteristics

7.2.2 Low-Dropout Voltage Regulator

7.2.3 Tradeoffs in LDO Regulators

7.3 Switched-Capacitor Converters

7.3.1 General Characteristics

7.3.2 Energy Efficiency

7.4 Switching DC-DC Converters

7.4.1 General Characteristics

7.4.2 Switching Buck Converter

7.4.3 Voltage Ripple

7.4.4 Energy Efficiency

7.5 Comparison of Voltage Regulators

7.6 On-Chip Power Conversion

7.6.1 Opportunities

7.6.2 Challenges

7.7 Chapter Summary

Chapter 8: Power Distribution Networks

8.1 Power Delivery and Power Supply Noise

8.1.1 Power Supply Noise

8.1.2 Effects of Power Supply Noise

8.1.3 Scaling Trends of Power Supply Noise

8.1.4 Power and Ground Distribution Systems

8.2 On-Chip Power Distribution Architectures

8.2.1 Routed Networks

8.2.2 Irregular Mesh Structured Networks

8.2.3 Regular Grid Structured Networks

8.2.4 Power and Ground Planes

8.2.5 Cascaded Power and Ground Rings

8.2.6 Hybrid Power and Ground Networks

8.3 Output Impedance Characteristics

8.3.1 Target Impedance

8.3.2 Decoupling Capacitance and Resonance

8.3.3 Types of On-Chip Decoupling Capacitors

8.3.4 Dependence of Impedance on Power Grid Type

8.4 Chapter Summary

Chapter 9: Computer-Aided Design and Analysis

9.1 Design Flow for On-Chip Power Networks

9.1.1 Pre-Floorplan Stage

9.1.2 Post-Floorplan Stage

9.1.3 Post-Layout Stage

9.2 Modeling RLC Impedance

9.3 Estimating Decoupling Capacitance

9.3.1 Analytic Technique

9.3.2 Simulation Based Technique

9.4 Characterizing the Load Circuit

9.4.1 Utilizing Passive Devices

9.4.2 Utilizing Piecewise Linear Current Sources

9.4.3 Dependence on Input Switching Pattern

9.5 On-Chip Power/Ground Noise Analysis

9.5.1 Static Analysis

9.5.2 Dynamic Analysis

9.5.3 Hierarchical Analysis

9.5.4 Statistical Analysis

9.6 Chapter Summary

Chapter 10: Techniques to Reduce Power Supply Noise

10.1 Noise Reduction at the Circuit Level

10.1.1 Topology and Wire Width Optimization

10.1.2 Decoupling Capacitor Placement

10.1.3 Exploiting the Damping Factor

10.1.4 Skew and Slew Rate Control

10.1.5 Opposite Phase Clock Tree

10.1.6 Spread Spectrum Clock Generation

10.2 Noise Reduction at System Level

10.2.1 Power Supply Noise Aware Floorplanning

10.2.2 Package and Board Characteristics

10.2.3 Asynchronous Circuit Design

10.3 Chapter Summary

Chapter 11: Power Dissipation

11.1 Transient Power Consumption

11.1.1 Dynamic Power

11.1.2 Short-Circuit Power

11.2 Static Power Consumption

11.2.1 Reverse Biased p-n Junction Leakage Current

11.2.2 Subthreshold Leakage Current

11.2.3 Modeling Subthreshold Current

11.2.4 Subthreshold Slope

11.2.5 Gate Oxide Tunneling Leakage Current

11.2.6 Gate Leakage Current Characteristics

11.2.7 High Permittivity Gate Dielectric Materials

11.2.8 High Permittivity Dielectric and Metal Gate

11.2.9 DC Power

11.3 Chapter Summary

Part IV: Synchronization

Chapter 12: Synchronization Theory and Tradeoffs

12.1 Classification of Boolean Signals

12.1.1 Isochronous versus Anisochronous Signals

12.1.2 Synchronous versus Asynchronous Signals

12.2 Fully Synchronous Circuit Operation

12.2.1 Timing Relationship

12.2.2 Advantages

12.2.3 Limitations

12.3 Self-Timed Circuit Operation

12.3.1 Timing Relationship

12.3.2 Advantages

12.3.3 Limitations

12.3.4 Fully Synchronous versus Self-Timed Systems

12.4 GALS Circuit Operation

12.4.1 Synchronizers in GALS Systems

12.4.2 Advantages

12.4.3 Limitations

12.5 Chapter Summary

Chapter 13: On-Chip Clock Generation

13.1 Ring Oscillators

13.1.1 Frequency Stability in Ring Oscillators

13.1.2 Multiphase Clock Generation

13.2 Crystal Oscillators

13.2.1 Crystal Resonator

13.2.2 Standard Crystal Oscillator

13.2.3 Pierce Oscillator

13.3 Phase-Locked Loops

13.3.1 PLLs in Digital Systems

13.3.2 System Level Characteristics

13.3.3 Phase Detector (PD)

13.3.4 Phase-Frequency Detector

13.3.5 Charge Pump

13.3.6 Loop Filter

13.3.7 Voltage-Controlled Oscillator

13.3.8 Frequency Response and PLL Loop Dynamics

13.4 Delay-Locked Loops

13.4.1 Operating Principle

13.4.2 Advantages

13.4.3 Frequency Response

13.4.4 Limitations

13.5 Chapter Summary

Chapter 14: Synchronous System Characteristics

14.1 Delay Components of a Data Path

14.1.1 Minimum Clock Period

14.1.2 Race Condition

14.2 Setup-Hold Times of a Register

14.3 Setup-Hold Time Characterization

14.3.1 Independent Setup-Hold Time Characterization

14.3.2 Interdependent Setup-Hold Time Characterization

14.4 Example of a Local Data Path

14.5 Clock Skew

14.5.1 Definition of Clock Skew

14.6 Timing Constraints

14.6.1 Timing Constraint for Long Data Paths

14.6.2 Timing Constraint for Short Data Paths

14.7 Enhancing Synchronous Performance

14.7.1 Example of Localized Negative Clock Skew

14.8 Chapter Summary

Chapter 15: On-Chip Clock Distribution

15.1 Clock Distribution Design

15.1.1 Buffered Clock Distribution Trees

15.1.2 Symmetric H-Tree Clock Distribution Networks

15.1.3 Compensation Techniques for Controlling Clock Skew

15.1.4 Design of Low Power Clock Distribution Networks

15.2 Automated Layout and Synthesis

15.2.1 Automated Clock Distribution Layout

15.2.2 Automated Clock Distribution Synthesis

15.2.3 Retiming

15.3 Analysis and Modeling

15.3.1 Process Insensitive Clock Distribution Networks

15.3.2 Models for Estimating Clock Skew

15.4 Clock Skew Scheduling

15.4.1 Off-Chip Clock Skew

15.4.2 Global and Local Timing Constraints

15.4.3 Example

15.5 Industrial Clock Distribution Networks

15.5.1 The Bell Telephone WE32100 32-Bit Microprocessor

15.5.2 The DEC/Compaq 64-Bit Alpha Microprocessor

15.5.3 8 Bit × 8 Bit Pipelined Multiplier

15.5.4 The Intel IA-64 Microprocessor

15.6 Chapter Summary

Part V: Substrate-Aware Design

Chapter 16: Substrate Noise in Mixed-Signal Systems

16.1 Switching Noise Coupling Mechanisms

16.1.1 Interconnect Coupling

16.1.2 Substrate Coupling

16.1.3 Substrate Noise Injection Mechanisms

16.2 Computer-Aided Design and Analysis

16.2.1 Substrate Extraction Techniques

16.2.2 Compact Substrate Models

16.2.3 High Level Substrate Noise Analysis

16.3 Effects of Substrate Noise

16.3.1 Low Noise Amplifier

16.3.2 Phase-Locked Loop

16.3.3 Sigma-Delta Data Converter

16.4 Chapter Summary

Chapter 17: Techniques to Reduce Substrate Noise

17.1 Noise Reduction at the Circuit Level

17.1.1 Biasing Methodologies

17.1.2 Differential Signaling

17.2 Noise Reduction at the Physical Level

17.2.1 Physical Separation

17.2.2 Guard Rings

17.3 Noise Reduction at the Technology Level

17.3.1 Deep N-Well Isolation

17.3.2 Silicon-on-Insulator Technology

17.4 Chapter Summary

Conclusions and Final Remarks

Bibliography

Index