Embedded Systems Hardware for Software Engineers

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Embedded Systems Hardware for Software Engineers

Embedded Systems Hardware for Software Engineers

Authors: Ed Lipiansky

Published: November 2011

eISBN: 9780071639491 0071639497 | ISBN: 9780071639484

Contents

Preface

1 Introduction to Embedded Systems

1.1 What Is an Embedded System?

1.2 What Is the Embedded Hardware?

1.3 Everyday Examples of Embedded Hardware

1.4 Embedded System Design Process: The Hardware Perspective

1.5 Summary

1.6 References

2 Real Machines: Architecture Examples

2.1 Microchip PIC32 Micro Controller Unit (MCU)

2.2 PIC32 Architecture Overview

2.3 PIC32 Programming Model

2.3.1 PIC32 CPU Instruction Formats

2.3.2 PIC32 CPU Registers

2.3.3 PIC32 CPU Modes of Operation

2.3.4 PIC32 Virtual Address Map

2.4 Atmel AVR32 Micro Controller Unit

2.5 AVR32 Architecture Overview: Feature Summary

2.5.1 Microarchitectures

2.6 AVR32 Programming Model

2.6.1 AVR32 CPU Instruction Formats

2.6.2 AVR32 CPU Registers

2.6.3 AVR32 CPU Modes of Operation

2.6.4 AVR32 Virtual Memory Space Map

2.7 Freescale Semiconductor’s M68K Microprocessor

2.7.1 Memory Organization

2.8 M68K Architecture Overview

2.9 M68K Programming Model

2.9.1 M68K CPU Instruction Formats

2.9.2 M68K CPU Registers and CPU Modes of Operation

2.10 Summary

2.11 References and Further Reading

3 Embedded Hardware

3.1 Embedded Hardware Building Block Selection

3.2 What Are Block Diagrams?

3.3 What Are Schematics?

3.4 Summary of Differences between Block Diagrams and Schematics

3.5 Differences between Microcontrollers and Microprocessors

3.6 A Handful of Very Popular Microprocessors

3.7 A Couple of Very Popular Microcontrollers

3.8 Von Neumann and Harvard Architectures

3.9 Complex Instruction Set Computers (CISCs)

3.10 Reduced Instruction Set Computers (RISCs)

3.11 Microprocessor and Microcontroller Selection

3.12 Summary

3.13 References and Further Reading

4 Memories

4.1 Main Memories

4.2 Cache Memories

4.2.1 Cache Details

4.2.2 Cache Fundamental Questions

4.3 Memory Devices

4.4 Random Access Memory (RAM)

4.5 Dynamic RAM (DRAM)

4.5.1 Asynchronous DRAM Operation and Timing

4.6 Dual Data Rate DRAM and Next Generations

4.6.1 DDR Commands

4.6.2 CAS Latency and Read Command

4.6.3 Write Burst Command

4.6.4 Subsequent DDR Generations: DDR2 and DDR3

4.7 Summary

4.8 References and Further Reading

5 Memory Address Decoding

5.1 Introduction

5.2 Address Decoding

5.2.1 How to Connect Address Lines

5.3 Summary

5.4 References and Further Reading

6 Read-Only Memories and Other Related Devices

6.1 Read-Only Memory (ROM)

6.2 Mask ROM

6.3 PROM, EPROM, and EEPROM

6.4 Programmable Logic Devices: PALs and PLAs

6.5 Flash Memories

6.5.1 NAND Flash Technology

6.5.2 Differences between NOR and NAND Flash Cells

6.6 A Word about Component Selection

6.7 Summary

6.8 References and Further Reading

7 Input and Output Ports

7.1 Elements of Input and Output Ports Interfacing

7.1.1 Read Operation

7.1.2 Write Operation

7.2 Interfacing Switches and Debouncing

7.3 Parallel Output Port

7.4 Bidirectional Input and Output Port

7.5 Interrupts

7.5.1 Supervisor and User Modes

7.5.2 Exception Processing

7.6 An Interrupt Controller Design Example: Its I/O Interface

7.7 Summary

7.8 References and Further Reading

8 Data Acquisition Components: Analog-to-Digital and Digital-to-Analog Converters

8.1 Introduction

8.2 The Analog-to-Digital Converter as a Circuit Element

8.2.1 Real ADC Most Common Errors

8.3 The Digital-to-Analog Converter as a Circuit Element

8.3.1 Real DAC Most Common Errors

8.4 Sampling Theorem and Minimum Sampling Frequency

8.4.1 Transforms

8.4.2 The Sampling Theorem

8.4.3 The Sampling Theorem and Aliasing Effects

8.5 Antialiasing and Reconstruction Filters

8.6 Data Acquisition Design Example

8.6.1 Sample-and-Hold Amplifier

8.7 Summary

8.8 References and Further Reading

9 Interfacing to External Devices

9.1 Introduction to Network Interfacing

9.2 The Asynchronous Serial Interface and RS-232C Standard

9.3 The Synchronous Serial Interface and RS-422/RS-485

9.3.1 RS-422 and RS-485 Electrical Standards

9.3.2 Topologies: Point-to-Point, Multidrop, and Multipoint

9.4 The I[sup(2)]C Two-Wire Serial Interface

9.4.1 Some I[sup(2)]C Bus Concepts

9.4.2 START and STOP Conditions

9.4.3 Serial Bus Transactions: Single-Byte Data Write

9.4.4 Single-Byte Data Read

9.4.5 Multibyte Data Write

9.4.6 Multibyte Data Read

9.5 The Universal Serial Bus (USB)

9.5.1 USB Bus Topology

9.5.2 Physical and Electrical Characteristics

9.6 Summary

9.7 References and Further Reading

10 Transmission Line Basics

10.1 What Is a Transmission Line?

10.2 Some Common Transmission Lines

10.2.1 Transmission Line Interconnect Types

10.3 Transmission Line Electrical Parameters

10.4 Unmatched Transmission Line Responses

10.5 Terminated Transmission Line Responses

10.6 Time-Domain Reflectometers (TDRs)

10.7 Measurements and Eye Patterns

10.8 Summary

10.9 References and Further Reading

11 Logic Families of Integrated Circuits and Their Signaling Characteristics

11.1 TTL Gate Output Implementations

11.1.1 Totem Pole Outputs

11.1.2 TTL Open Collector and Open Drain Outputs

11.1.3 Tristate Outputs

11.2 Three Pillars of Digital Technology

11.3 Transistor-Transistor Logic (TTL) and I/O Levels

11.4 Complementary Metal-Oxide Semiconductor (CMOS) and I/O Levels

11.4.1 CMOS Logic Levels

11.4.2 CMOS Logic Examples

11.5 Emitter Coupled Logic (ECL) and I/O Levels

11.6 ECL Termination Schemes

11.7 Bipolar and CMOS (BiCMOS) I/O Levels

11.7.1 Some BiCMOS Technology Components

11.8 Summary

11.9 References and Further Reading

12 The Printed-Circuit Board (PCB)

12.1 What Is a PCB?

12.2 Single- and Double-Layer Boards

12.3 Multilayer Boards

12.4 PCB Interconnects: Traces

12.4.1 Microstrips

12.4.2 Strip Lines

12.4.3 Differential Traces

12.5 Stack-up Design

12.6 Some Commonly Used Materials

12.7 General Placement and Routing Guidelines for High-Speed Designs

12.7.1 Placement

12.7.2 Routing

12.8 Summary

12.9 References and Further Reading

13 Programmable Logic Devices

13.1 Complex Programmable Logic Devices (CPLDs)

13.1.1 Xilinx CoolRunner-II CPLD Architecture

13.1.2 Xilinx CoolRunner-II CPLD Input-Output (I/O) Block Architecture

13.2 Field-Programmable Gate Arrays (FPGAs)

13.2.1 Configurable Logic Block

13.2.2 Input-Output Block

13.2.3 Programmable Routing Matrix

13.3 Summary

13.4 References and Further Reading

14 Test Equipment: Oscilloscopes and Logic Analyzers

14.1 Oscilloscopes

14.2 Real-Time Sampling Oscilloscopes

14.3 Equivalent Time Sampling Oscilloscopes

14.4 Logic Analyzer (LA)

14.4.1 LA Operation and Mode Selection

14.4.2 LA Triggering Capabilities

14.4.3 LA Features

14.5 Other Basic Test Equipment

14.6 Summary

14.7 References and Further Reading

Index