Semiconductor Process Reliability in Practice

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Semiconductor Process Reliability in Practice

Semiconductor Process Reliability in Practice

Authors: Zhenghao Gan, Waisum Wong and Juin Liou

Published: October 2012

eISBN: 9780071754286 0071754288 | ISBN: 9780071754279

Cover

About the Authors

Title Page

Copyright Page

Contents

Part 1: General

Chapter 1: Introduction

1.1 Background

1.2 Process Reliability Items

1.2.1 FEOL

1.2.2 BEOL

1.3 Process-Dependent Reliability

1.4 Reliability Assessment Methodology

1.5 Organization of This Book

1.6 References

Chapter 2: Basic Device Physics

2.1 Basic Material Property Introduction

2.1.1 Conductors, Semiconductors, and Insulators

2.1.2 Electron and Hole Energies

2.1.3 Collision and Energy Exchange in Semiconductors

2.2 PN Junctions

2.2.1 The Energy Band of PN Junctions

2.2.2 PN Junctions with Bias

2.2.3 Junction Capacitance

2.3 Basic Physics of Metal-Oxide-Semiconductor Capacitors

2.3.1 The Energy Band of Metal-Oxide-Semiconductor Capacitors

2.3.2 Metal-Oxide-Semiconductor Capacitor Capacitance-Voltage Curve

2.4 Physics of Metal-Oxide-Semiconductor Field-Effect Transistors

2.4.1 The Current-Voltage Characteristics of the Metal-Oxide-Semiconductor Field-Effect Transistor

2.4.2 Long-Channel Vt of the Metal-Oxide-Semiconductor Field-Effect Transistor

2.4.3 The Capacitances in a Metal-Oxide-Semiconductor Field-Effect Transistor

2.5 The Secondary Effects of Metal-Oxide-Semiconductor Field-Effect Transistors

2.5.1 Short-Channel Effect

2.5.2 Width Effect

2.5.3 Gate-Induced Drain Leakage

2.5.4 Boron Penetration

2.5.5 Effect of Substrate Bias

2.6 Interface Traps and Oxide Traps

2.7 References

Chapter 3: Process Flow for Metal-Oxide-Semiconductor Manufacturing

3.1 Front-End-of-Line

3.2 Back-End-of-Line of the Cu Dual Damascene Processes

3.3 References

Chapter 4: Measurements Useful for Device Reliability Characterization

4.1 Capacitance-Voltage Measurement

4.2 Direct-Current Current-Voltage

4.2.1 Extraction of Interface Trap from Direct-Current Current-Voltage Measurement

4.2.2 Extraction of Oxide Traps from the Direct-Current Current-Voltage Measurement

4.3 Gated-Diode Method

4.4 Charge-Pumping Measurement

4.5 Midgap Measurement for Interface and Oxide Trap Separation

4.6 Carrier-Separation Measurement

4.7 Current-Voltage Characteristics

4.8 References

Part 2: Front-End-of-Line

Chapter 5: Hot-Carrier Injection

5.1 Maximum Channel Electrical Field

5.2 HCI Physical Mechanisms

5.2.1 Field-Driven CHC Mechanisms

5.2.2 Energy-Driven Channel-Hot-Carrier Mechanism: Electron-Electron Scattering

5.2.3 Multiple-Vibrational-Excitation Mechanism

5.2.4 NMOS Hot-Carrier-Injection Mechanisms/Models

5.2.5 PMOS Hot-Carrier-Injection Mechanisms/Models

5.3 Hot-Carrier-Injection Characterization Methodology

5.3.1 Device Parameters to Monitor

5.3.2 Hot-Carrier-Injection Degradation Models

5.3.3 Lifetime Extrapolation

5.4 Screening Effect on Hot-Carrier-Injection Characterization

5.5 Hot-Carrier-Injection Degradation Saturation

5.6 Temperature Effect on Hot-Carrier Injection

5.7 Effect of Bulk Bias on Hot-Carrier Injection

5.8 Effects of Structure on Hot-Carrier Injection

5.8.1 Effect of Channel Width on Hot-Carrier Injection

5.8.2 Effect of Channel Length on Hot-Carrier Injection

5.8.3 Effect of Offset Spacers on Hot-Carrier Injection

5.8.4 Effect of Spacing Between the Gate Edge and the Shallow-Trench Isolation Edge

5.9 Process Effects on Hot-Carrier Injection Performance

5.9.1 Drain Engineering

5.9.2 Gate-Oxide Robustness

5.10 Hot-Carrier Injection Qualification Practice

5.11 References

Chapter 6: Gate-Oxide Integrity and Time-Dependent Dielectric Breakdown

6.1 Tunneling in Metal-Oxide-Semiconductor Structure

6.1.1 Gate Leakage Tunneling Mechanism

6.1.2 Polarity-Dependent Qbd and Tbd

6.1.3 Relationship Between Gate Leakage Current and Vbd/Tbd

6.2 Gate-Oxide Dielectric Breakdown Mechanism

6.2.1 Extrinsic versus Intrinsic Breakdown

6.2.2 Time-Dependent Dielectric Breakdown

6.2.3 Correlation Between Vbd and Tbd

6.2.4 Models for Defect Generation

6.2.5 Soft Breakdown

6.3 Stress-Induced Leakage Current

6.4 Gate-Oxide-Integrity Test Structures and Failure Analysis

6.4.1 Bulk Structure

6.4.2 Poly-Edge-Intensive Structure

6.4.3 Shallow-Trench-Isolation-Edge-Intensive Structure

6.4.4 Shallow-Trench-Isolation-Corner-Intensive Structure

6.4.5 Failure Analysis for Gate-Oxide Integrity

6.5 Gate-Oxide Time-Dependent Dielectric-Breakdown Models, Lifetime Extrapolation Methodology

6.5.1 Weibull Distribution

6.5.2 Activation Energy

6.5.3 1/E Model, E Model, V Model, and Power-Law Model

6.5.4 Area Scaling

6.6 Process Effects on Gate-Oxide Integrity and Time-Dependent Dielectric Breakdown Improvement

6.6.1 Effect of Oxide Thickness

6.6.2 Effect of Nitridation

6.6.3 Effect of Hydrogen/D2

6.6.4 Metal Contamination

6.6.5 Effect of Poly Grain Structure

6.6.6 Effect of Poly Profile (Poly Footing)

6.6.7 Effect of Gate-Oxide Preclean and Etch

6.6.8 Effect of Annealing Environment after Sacrificial Oxidation

6.6.9 Effect of Sacrificial-Oxide-Free

6.6.10 Effect of the Adhesion of Photoresist

6.6.11 Effect of Indium Implantation

6.6.12 Process Factors on the Power-Law Model Exponent

6.7 Process Qualification Practice

6.8 References

Chapter 7: Negative-Bias Temperature Instability

7.1 Negative-Bias Temperature Instability Degradation Mechanism

7.1.1 Reaction-Diffusion Model

7.1.2 Recovery

7.1.3 Degradation Saturation Mechanism

7.2 Degradation-Time Exponent n, Activation Energy Ea, and Voltage/Field Acceleration Factor f

7.2.1 Degradation-Time Exponent n

7.2.2 Activation Energy (Ea)

7.2.3 Voltage/Field Acceleration Factor g

7.3 Characterization Methodology

7.3.1 Delay-Time (Recovery) Effect on Characterization

7.3.2 Stress-Voltage and Stress-Time Effects

7.3.3 Uninterrupted-Stress Methods

7.3.4 Influence of Bulk Bias on Negative-Bias Temperature Instability

7.4 Why Is PMOS under Inversion the Worst?

7.5 Effect of Structure on Negative-Bias Temperature Instability

7.5.1 Channel Length Dependence

7.5.2 Channel Width Dependence

7.5.3 Gate-Oxide Thickness Dependence

7.6 Effects of Process on Negative-Bias Temperature Instability

7.6.1 Nitrogen and Its Profile

7.6.2 Incorporation of Fluorine

7.6.3 Gate-oxide and Si-SiO2-interface quality

7.6.4 H2/D2 anneal

7.6.5 Back-End-of-Line process

7.6.6 Effect of plasma-induced damage

7.6.7 Boron penetration

7.6.8 Effect of contact-etch stop layer

7.6.9 Effect of Si substrate orientation

7.7 Dynamic Negative-Bias Temperature Instability

7.8 Process Qualification Practice

7.9 References

Chapter 8: Plasma-Induced Damage

8.1 Introduction

8.2 Mechanisms for Plasma-Induced Damage

8.2.1 Plasma Density

8.2.2 Plasma Nonuniformity Across the Wafer

8.2.3 Electron-Shading Effect

8.2.4 Reverse Electron-Shading Effect

8.2.5 Ultraviolet Radiation

8.3 Plasma-Induced Damage Characterization Methodology

8.4 Plasma Characteristics

8.4.1 Plasma Characterization Methodology

8.4.2 Plasma I-V Characteristics and Plasma Parameter Effects on Plasma I-V and Damage

8.5 Effect of Substrate on Plasma-Induced Damage

8.5.1 Why PMOS Is Worse Than NMOS

8.5.2 Effect of Protection Devices

8.5.3 Effect of Gate-Oxide Thickness on Plasma-Induced Damage

8.5.4 Effect on Silicon-on-Insulator Devices

8.5.5 Antenna Attached to the Source/Drain and the Substrate

8.5.6 Effect of Well Configuration

8.6 Effect of Structures on Plasma-Induced Damage

8.6.1 Effect of Antenna Finger Density

8.6.2 Avoiding Plasma-Induced Damage Through a Bridging Design

8.6.3 Latent Antenna Effect

8.6.4 Spreading Antenna Effect

8.6.5 Capacitor versus Transistor as Detector

8.7 Process Effect on Plasma-Induced Damage

8.7.1 Effect of Anneal on Process-Induced Damage to the Gate Oxide

8.7.2 Effect of Passivation Etch

8.7.3 Effect of SiN Cap NH3 Plasma Pretreatment Process on Plasma-Induced Damage

8.7.4 Effect of Plasma Parameters on Plasma-Induced Damage

8.7.5 Premetal Dielectric Deposition

8.7.6 Effect of Intermetallic Etch and Via Etch

8.7.7 Effect of Process Temperature

8.7.8 Reducing Plasma Charge Damage by Equipment Modification

8.7.9 Progressive Deterioration Characteristics of Plasma-Induced Damage

8.7.10 Gate-Oxide Robustness

8.7.11 Effect of Intermetallic Dielectric Deposition

8.7.12 Effect of Barrier/Seed Deposition

8.7.13 Insulating Layer at the Backside of the Wafer

8.8 Other Reliability Issues Related to Plasma-Induced Damage

8.8.1 Hot-Carrier Injection

8.8.2 Negative-Bias Temperature Instability

8.8.3 Gate-Oxide Integrity

8.9 Process-Qualification Practice

8.10 References

Chapter 9: Electrostatic Discharge Protection of Integrated Circuits

9.1 Background of Electrostatic Discharge Events

9.2 Modeling of Electrostatic-Discharge-Protection Device

9.2.1 Physical Behavior of NMOS Devices with Parasitic Bipolar Transistors

9.2.2 Development of a Compact Model for Electrostatic Discharge

9.2.3 Model Implementation in SPICE

9.2.4 Results and Discussion

9.2.5 Advanced Metal-Oxide-Semiconductor Models

9.3 Electrostatic-Discharge Measurements and Testing

9.3.1 Experimental Setup for Electrostatic-Discharge Measurements Based on the Transmission-Line-Pulsing Technique

9.3.2 Development of a Matched-Load Circuit

9.3.3 Determination of Transmission-Line Pulse Width Equivalent to the Human-Body Model

9.4 Design of On-Chip Electrostatic-Discharge Protection Solutions

9.4.1 Electrostatic-Discharge Design Based on Silicon-Controlled Rectifiers

9.4.2 Electrostatic-Discharge-Protection Design Based on the Diode

9.4.3 Radio Frequency Optimization

9.5 References

Part 3: Back-End-of-Line

Chapter 10: Electromigration

10.1 Physics of Electromigration

10.2 Electromigration Characterization

10.2.1 Package-Level Reliability versus Wafer-Level Reliability

10.2.2 Metal-Line Test Structures

10.2.3 Critical-Length Test Structures

10.2.4 Drift-Velocity Test Structure

10.2.5 Heat-Generation Test Structures

10.2.6 Two-Level Via-Involved Test Structures

10.3 Time-to-Failure in Electromigration

10.3.1 Black’s Equation (Two-Parameter Lognormal Distribution)

10.3.2 Bimodal Lognormal Distribution

10.3.3 Three-Parameter Lognormal Distribution

10.4 Electromigration Failure Modes

10.5 Understanding of Electromigration Mechanisms

10.5.1 Electromigration at Contact

10.5.2 Electromigration at Al and W Vias

10.5.3 Electromigration at Cu Interconnects

10.6 Process Effect on Electromigration

10.6.1 Cu/Low-k Interaction, Cu/Low-k Interface Control

10.6.2 Control of Cu-Interconnect Microstructure

10.6.3 Barrier/Seed-Layer Effect

10.6.4 Effect of Solute/Doping on Electromigration

10.6.5 Effect of Dual-Damascene Structure Profile

10.6.6 Effect of Oxygen Content on Cu Interconnects

10.6.7 Effect of Preexisting Voids on Electromigration

10.7 Effect of Structures on Electromigration

10.7.1 Via/Line Interconnection Configuration

10.7.2 Reservoir Effect (Line-Extension Effect)

10.7.3 Metal Critical-Length Effect

10.7.4 Metal Thickness/Width Dependence

10.8 Electromigration under Alternating-Current Conditions

10.8.1 Definition of Peak, Average, and rms Current Densities

10.8.2 Characterization of Jrms

10.9 Process-Qualification Practice

10.10 References

Chapter 11: Stress Migration

11.1 Introduction

11.2 Physics of Stress Migration

11.2.1 Basic Understanding of the Stress Migration Mechanism

11.2.2 Active Diffusion Volume

11.2.3 Void nucleation

11.2.4 Stress Gradient

11.2.5 N ew failure mechanism observed for stress migration

11.2.6 Mathematical model for Stress-Induced Voiding

11.3 Characterization of Stress Migration

11.3.1 Stress-Migration test structures

11.3.2 Stress-Migration characterization methodology

11.4 Failure Modes of Stress Migration

11.5 Finite-Element Method for Stress Migration

11.5.1 Finite-Element-Method model description

11.5.2 F inte-Element-Method parameters to characterize stress and examples

11.6 Process Effects on Stress Migration

11.6.1 Via-Gouging Effect

11.6.2 Metallization-Layer Dependence

11.6.3 Barrier-layer effect

11.6.4 Cu Alloy Effect

11.6.5 Dielectric dependence

11.6.6 Copper-Microstructure Effect

11.6.7 Quenching Effect

11.6.8 Copper-Plating Chemistry

11.6.9 Cu-capping-layer effect

11.6.10 Miscellaneous

11.7 Geometric Effect on Stress Migration (Stress-Migration Improvement T hrough Design)

11.7.1 Effect of Metal Plate Geometry

11.7.2 Effect of via misalignment

11.7.3 Effect of dielectric slots

11.7.4 Dual (multiple) Via Effect

11.8 Process-Qualification Practices

11.9 References

Chapter 12: Intermetal Dielectric Breakdown

12.1 Introduction

12.2 Test Structures and Test Methodology

12.2.1 Test Structures

12.2.2 Test Methodology

12.3 Failure Mechanisms/Modes for Intermetal Dielectric Breakdown

12.3.1 Failure Mechanisms

12.3.2 Failure Modes

12.4 Lifetime Models

12.4.1 Weibull Distribution

12.4.2 1/E Model, E Model, and SQRT(E) Model

12.4.3 Activation Energy

12.4.4 Area/Length Scaling

12.4.5 Defect Density (DD

12.5 Factors Affecting IMD Reliability

12.5.1 Material Dependence

12.5.2 Moisture Effect

12.5.3 Critical-Dimension (CD) Control

12.5.4 Cu-Cap Interface Quality Control

12.5.5 Novel Cap Layers

12.5.6 Barrier Effect

12.5.7 Self-Assembled Molecular Nanolayers as Diffusion Barrier

12.5.8 Cu CMP Effect

12.6 Correlation Between Voltage-Ramp (Vbd) and Time-Dependent Dielectric Breakdown (Tbd)

12.7 Time-Dependent Dielectric Breakdown Characteristics for Stacked-Via-Involved Comb Structures

12.8 Finite-Element Modeling for Dielectric Reliability Assessment

12.8.1 Finite-Element Modeling for Electric Field Simulation

12.8.2 Finite-Element Model for k-Value Extraction of Low-k Material

12.8.3 Finite-Element Model for k-Drift of Low-k Dielectric Materials

12.8.4 Finite-Element Model for Process-Induced Damage Evaluation

12.9 Process-Qualification Practice

12.10 References

Index