Through-Silicon Vias for 3D Integration

Home >
Browse >
Through-Silicon Vias for 3D Integration

Through-Silicon Vias for 3D Integration

Authors: John Lau

Published: September 2012

eISBN: 9780071785150 0071785159 | ISBN: 9780071785143

Cover

About the Author

Title Page

Copyright Page

Contents

Foreword

Preface

Acknowledgments

Chapter 1: Nanotechnology and 3D Integration for the Semiconductor Industry

1.1 Introduction

1.2 Nanotechnology

1.2.1 Origin of Nanotechnology

1.2.2 Important Milestones of Nanotechnology

1.2.3 Why Graphene Is So Exciting and Could Be Very Important for the Electronics Industry

1.2.4 Outlook of Nanotechnology

1.2.5 Moore’s Law: Nanotechnology for the Electronics Industry

1.3 Three-Dimensional Integration

1.3.1 Through-Silicon Via Technology

1.3.2 Origin of 3D Integration

1.4 Challenges and Outlook of 3D Si Integration

1.4.1 3D Si Integration

1.4.2 3D Si Integration Bonding Assembly

1.4.3 3D Si Integration Challenges

1.4.4 3D Si Integration Outlook

1.5 Potential Applications and Challenges of 3D IC Integration

1.5.1 Definition of 3D IC Integration

1.5.2 Future Requirements of Mobile Products

1.5.3 Definition of Bandwidth and Wide I/O

1.5.4 Memory Bandwidth

1.5.5 Memory-Chip Stacking

1.5.6 Wide I/O Memory

1.5.7 Wide I/O DRAM

1.5.8 Wide I/O Interface

1.5.9 2.5D and 3D IC Integration (Passive and Active Interposers)

1.6 Recent Advances of 2.5D IC Integration (Interposers)

1.6.1 Interposer Used as Intermediate Substrate

1.6.2 Interposer Used as a Stress-Relief (Reliability) Buffer

1.6.3 Interposer Used as Carrier

1.6.4 Interposer Used as a Thermal Management Tool

1.7 New Trends in TSV Passive Interposers for 3D IC Integration

1.7.1 Interposer (with a Cavity) Supporting High-Power Chips on Its Top Side and Low-Power Chips on Its Bottom Side

1.7.2 Interposer (on an Organic Substrate with a Cavity) Supporting High-Power Chips on Its Top Side and Low-Power Chip Stacking on Its Bottom Side

1.7.3 A Simple Design Example

1.7.4 Interposer (on an Organic Substrate with a Cavity) Supporting High-Power Chips on the Top Side and Low-Power Chips (with Heat Slug/Spreader) on the Bottom Side

1.7.5 Ultralow-Cost Interposer for 3D IC Integration

1.7.6 Interposer Used as a Thermal Management Tool for 3D IC Integration

1.7.7 Interposer with Embedded Fluidic Microchannels for 3D Light-Emitting Diode and IC Integration SiP

1.8 Embedded 3D IC Integration

1.8.1 Semiembedded Interposer with Stress-Relief Gap

1.8.2 Embedded 3D Hybrid IC Integration for Optoelectronic Interconnects

1.9 Summary and Recommendations

1.10 TSV Patents

1.11 References

1.12 General Readings

1.12.1 TSV and 3D Integration and Reliability

1.12.2 3D MEMS and IC Integration

1.12.3 Semiconductor IC Packaging

Chapter 2: Through-Silicon Via Technology

2.1 Introduction

2.2 Who Invented TSV and When

2.3 High-Volume Products with TSV Technology

2.4 Via Forming

2.4.1 DRIE versus Laser Drilling

2.4.2 Tapered Via by DRIE

2.4.3 Straight Via by DRIE

2.5 Dielectric Isolation Layer (Oxide Liner) Deposition

2.5.1 Tapered Oxide Liner by Thermal Oxidation

2.5.2 Tapered Oxide Liner by PECVD

2.5.3 DoE for Straight Oxide Liner by PECVD

2.5.4 DoE Results for Straight Oxide Liner by PECVD

2.5.5 Summary and Recommendations

2.6 Barrier (Adhesion) Layer and Seed (Metal) Layer Deposition

2.6.1 Tapered TSV with Ti Barrier Layer and Cu Seed Layer

2.6.2 Straight TSV with Ta Barrier Layer and Cu Seed Layer

2.6.3 Straight TSV with Ta Barrier Layer Experiments and Results

2.6.4 Straight TSV with Cu Seed Layer Experiments and Results

2.6.5 Summary and Recommendations

2.7 TSV Filling by Cu Plating

2.7.1 Cu Plating to Fill Tapered TSVs

2.7.2 Cu Plating to Fill Straight TSVs

2.7.3 Leakage-Current Test of Blind Straight TSVs

2.7.4 Summary and Recommendations

2.8 Chemical-Mechanical Polishing of Cu Plating Residues

2.8.1 CMP for Tapered TSVs

2.8.2 CMP for Straight TSVs

2.8.3 Summary and Recommendations

2.9 TSV Cu Reveal

2.9.1 TSV Cu Reveal by CMP (Wet Process)

2.9.2 Cu Reveal by Dry Etching Process

2.9.3 Summary and Recommendation

2.10 FEOL and BEOL

2.11 TSV Processes

2.11.1 Via-Before Bonding Process

2.11.2 Via-After Bonding Process

2.11.3 Via-First Process

2.11.4 Via-Middle Process

2.11.5 Via-Last (From the Front Side) Process

2.11.6 Via-Last (From the Backside) Process

2.11.7 How About the Passive Interposers?

2.11.8 Summary and Recommendations

2.12 References

Chapter 3: Through-Silicon Vias: Mechanical, Thermal, and Electrical Behaviors

3.1 Introduction

3.2 Mechanical Behavior of TSVs in System-in-Package

3.2.1 Mechanical Behavior of TSVs for Active/Passive Interposers

3.2.2 DFR Results

3.2.3 TSVs with a Redistribution Layer

3.2.4 Summary and Recommendations

3.3 Mechanical Behavior of TSVs in Memory-Chip Stacking

3.3.1 Boundary-Value Problem

3.3.2 Nonlinear Thermal Stress Analyses for TSVs

3.3.3 Modified Virtual Crack-Closure Technique

3.3.4 Energy Release Rate Estimation for TSVs

3.3.5 Parametric Study of Energy Release Rate for TSVs

3.3.6 Summary and Recommendations

3.4 Thermal Behaviors of TSVs

3.4.1 Equivalent Thermal Conductivity of TSV Chip/Interposer

3.4.2 Effect of TSV Pitch on Equivalent Thermal Conductivity of Chip/Interposer

3.4.3 Effect of TSV Filler on Equivalent Thermal Conductivity of Chip/Interposer

3.4.4 Effect of Plating Thickness of a Partially Cu-Filled TSV Interposer/Chip on the Equivalent Thermal Conductivity

3.4.5 More Accurate Models

3.4.6 Summary and Recommendations

3.5 Electrical Modeling of TSVs

3.5.1 Definition

3.5.2 The Model and Equations

3.5.3 Summary and Recommendations

3.6 Electrical Test of Blind TSVs

3.6.1 Motivation

3.6.2 Testing Principle and Apparatus

3.6.3 Experimental Procedures, Measurements, and Results

3.6.4 Blind TSV Electrical Test Guidelines

3.6.5 Summary and Recommendations

3.7 References

Chapter 4: Thin-Wafer Strength Measurement

4.1 Introduction

4.2 Piezoresistive Stress Sensors for Thin-Wafer Strength Measurement

4.2.1 Problem Definition

4.2.2 Design and Fabrication of Piezoresistive Stress Sensors

4.2.3 Calibration of Stress Sensors

4.2.4 Stresses in Wafers after Thinning (Back-Grinding)

4.2.5 Stresses in Wafers after Mounting on Dicing Tape

4.2.6 Summary and Recommendations

4.3 Effects of Wafer Back-Grinding on the Mechanical Behavior of Cu–Low-k Chips

4.3.1 Problem Definition

4.3.2 Experiments

4.3.3 Results and Discussion

4.3.4 Summary and Recommendations

4.4 References

Chapter 5: Thin-Wafer Handling

5.1 Introduction

5.2 Wafer Thinning and Thin-Wafer Handling

5.3 Adhesive Is the Key

5.4 Thin-Wafer Handling Issues and Potential Solutions

5.4.1 Thin-Wafer Handling of 200-mm Wafers

5.4.2 Thin-Wafer Handling of 300-mm Wafers

5.5 Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu/Au Pads

5.6 Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu-Ni-Au UBMs

5.7 Effect of Dicing Tape on Thin-Wafer Handling of Interposer with RDLs and Ordinary Solder Bumps

5.8 Materials and Equipments for Thin-Wafer Handling

5.9 Adhesive and Process Guidelines for Thin-Wafer Handling

5.9.1 Some Requirements for Selecting Adhesives

5.9.2 Some Process Guideline for Thin-Wafer Handling

5.10 Summary and Recommendations

5.11 3M Wafer Support System

5.12 EVG’s Temporary Bonding and Debonding System

5.12.1 Temporary Bonding

5.12.2 Debonding

5.13 Thin-Wafer Handling with Carrierless Technology

5.13.1 The Idea

5.13.2 The Design and Process

5.13.3 Summary and Recommendations

5.14 References

Chapter 6: Microbumping, Assembly, and Reliability

6.1 Introduction

Part A Can we apply the Wafer Bumping Method of Ordinary Solder Bumps to Solder Microbumps

6.2 Problem Definition

6.3 Electroplating Method for Wafer Bumping of Ordinary Solder Bumps

6.4 Assembly of 3D IC Integration SiPs

6.5 Electroplating Method for Wafer Bumping of Solder Microbumps

6.5.1 Test Vehicle

6.5.2 Wafer Microbumping of the Test Wafer by Conformal Cu Plating and Electroplating Sn

6.5.3 Wafer Microbumping of the Test Wafer by Nonconformal Cu Plating and Electroplating of Sn

6.6 Can We Apply the Same Parameters of the Electroplating Method for Ordinary Solder Bumps to Microbumps?

6.7 Summary and Recommendations

Part B Wafer Bumping, Assembly, and Reliability Assessments of Ultrafine-Pitch Solder Microbumps?

6.8 Lead-Free Fine-Pitch Solder Microbumping

6.8.1 Test Vehicle

6.8.2 Microbump Fabrication

6.8.3 Characterization of Microbumps

6.9 Lead-Free Fine-Pitch C2C Solder Microbump Assembly

6.9.1 Assembly, Characterization, and Reliability-Assessment Methods

6.9.2 Assembly Process (C2C Natural Reflow)

6.9.3 Characterization of C2C Reflow Assembly Results

6.9.4 Assembly Process (C2C Thermocompression Bonding)

6.9.5 Characterization of C2C TCB Assembly Results

6.9.6 Reliability Assessments of Assemblies

6.10 Wafer Bumping of Lead-Free Ultrafine-Pitch Solder Microbumps

6.10.1 Test Vehicle

6.10.2 Microbump Fabrication

6.10.3 Characterization of Ultrafine-Pitch Microbumps

6.11 Conclusions and Recommendations

6.12 References

Chapter 7: Microbump Electromigration

7.1 Introduction

7.2 Solder Microjoints with Larger Solder Volumes and Pitch

7.2.1 Test Vehicles and Methods

7.2.2 Test Procedures

7.2.3 Microstructures of Samples Before Tests

7.2.4 Samples Tested at 140çC with Low Current Density

7.2.5 Samples Tested at 140ºC with High Current Density

7.2.6 Failure Mechanism of the Multiphase Solder-Joint Interconnect

7.2.7 Summary and Recommendations

7.3 Solder Microjoints with Smaller Volumes and Pitches

7.3.1 Experimental Setup and Procedure

7.3.2 Results and Discussion

7.3.3 Summary and Recommendations

7.4 References

Chapter 8: Transient Liquid-Phase Bonding: Chip-to-Chip, Chip-to-Wafer, and Wafer-to-Wafer

8.1 Introduction

8.2 How Does Low-Temperature Bonding with Solder Work?

8.3 Low-Temperature C2C [(SiO2/Si3N4/Ti/Cu) to (SiO2/Si3N4/Ti/Cu/In/Sn/Au)] Bonding

8.3.1 Test Vehicle

8.3.2 Pull-Test Results

8.3.3 X-Ray Diffraction and Transmission Electron Microscope Observations

8.4 Low-Temperature C2C [(SiO2/Ti/Cu/Au/Sn/In/Sn/Au) to (SiO2/Ti/Cu/Sn/In/Sn/Au)] Bonding

8.4.1 Test Vehicle

8.4.2 Qualification Test Results

8.5 Low-Temperature C2W [(SiO2/Ti/Au/Sn/In/Au) to (SiO2/Ti/Au)] Bonding

8.5.1 Solder Design

8.5.2 Test Vehicle

8.5.3 3D IC Chip Stacking with InSnAu Low-Temperature Bonding

8.5.4 SEM, TEM, XDR, and DSC of the InSnAu IMCs

8.5.5 Young’s Modulus and Hardness of the InSnAu IMCs

8.5.6 Three Reflows of the InSnAu IMCs

8.5.7 Shear Strength of the InSnAu IMCs

8.5.8 Electrical Resistance of the InSnAu IMCs

8.5.9 When Does the InSnAu IMC Become Unstable?

8.5.10 Summary and Recommendations

8.6 Low-Temperature W2W [TiCuTiAu to TiCuTiAuSnInSnInAu] Bonding

8.6.1 Test Vehicle

8.6.2 Test Vehicle Fabrication

8.6.3 Low-Temperature W2W Bonding

8.6.4 C-SAM Inspection

8.6.5 Microstructure by SEM/EDX/FIB/TEM

8.6.6 Helium Leak-Rate Test and Results

8.6.7 Reliability Tests and Results

8.6.8 Summary and Recommendations

8.7 References

Chapter 9: Thermal Management of Three-Dimensional Integrated Circuit Integration

9.1 Introduction

9.2 Effects of TSV Interposer on Thermal Performance of 3D Integration SiPs

9.2.1 Geometry and Thermal Properties of Materials for Package Modeling

9.2.2 Effect of TSV Interposer on Package Thermal Resistance

9.2.3 Effect of Chip Power

9.2.4 Effect of Interposer Size

9.2.5 Effect of TSV Interposer Thickness

9.2.6 Effect of Moore’s Law Chip Size

9.3 Thermal Performance of 3D Memory-Chip Stacking

9.3.1 Thermal Performance of 3D Stacked TSV Chips with a Uniform Heat Source

9.3.2 Thermal Performance of 3D Stacked TSV Chips with a Nonuniform Heat Source

9.3.3 Two TSV Chips (Each with One Distinct Heat Source

9.3.4 Two TSV Chips (Each with Two Distinct Heat Sources)

9.3.5 Two TSV Chips with Two Staggered Distinct Heat Sources

9.4 Effect of Thickness of the TSV Chip on Its Hot-Spot Temperature

9.5 Summary and Recommendations

9.6 Thermal Management System with TSVs and Microchannels for 3D Integration SiPs

9.6.1 Test Vehicle

9.6.2 Test Vehicle Fabrication

9.6.3 Wafer-to-Wafer Bonding

9.6.4 Thermal and Electrical Performance

9.6.5 Quality and Reliability

9.6.6 Summary and Recommendations

9.7 References

Chapter 10: Three-Dimensional Integrated Circuit Packaging

10.1 Introduction

10.2 Cost: TSV Technology versus Wire-Bonding Technology

10.3 Wire Bonding of Stack Dies on Cu–Low-k Chips

10.3.1 Test Vehicles

10.3.2 Stresses at the Cu–Low-k Pads

10.3.3 Assembly and Process

10.3.4 Summary and Recommendations

10.4 Bare Chip-to-Chip and Face-to-Face Interconnects

10.4.1 3D IC Packaging with AuSn Interconnects

10.4.2 Test Vehicle and Fabrication

10.4.3 Chip-to-Wafer Assembly

10.4.4 C2W Design of Experiments (DoE)

10.4.5 Reliability Tests and Results

10.4.6 3D IC Packaging with SnAg Interconnects

10.4.7 Summary and Recommendations

10.5 Low-Cost, High-Performance, and High-Density SiPs with Face-to-Face Interconnects

10.5.1 Cu Wire-Interconnect Technology for Moore’s Law Chips with Ultrafine-Pitch Cu–Low-k Pads

10.5.2 Reliability Assessment of Ultrafine-Pitch Cu–Low-k Pads with Cu WIT

10.5.3 A Few New Design Proposals

10.6 Fan-Out-Embedded WLP-to-Chip (Face-to-Face) Interconnects

10.6.1 2D eWLP/RCP

10.6.2 3D eWLP/RCP

10.6.3 Summary and Recommendation

10.7 A Note on Wire-Bonding Reliability

10.7.1 Common Chip-Level Interconnects

10.7.2 Boundary-Value Problem

10.7.3 Numerical Results

10.7.4 Experimental Results

10.7.5 More Results on Cu Wires

10.7.6 Results on Au Wires

10.7.7 Stress-Strain Relationship of Cu and Au Wires

10.7.8 Summary and Recommendations

10.8 References

Chapter 11: Future Trends of 3D Integration

11.1 Introduction

11.2 The Trend of 3D Si Integration

11.3 The Trend of 3D IC Integration

11.4 References

Index