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Nanoscale CMOS VLSI Circuits: Design for Manufacturability
CITATION
Kundu, Sandip and
Sreedhar, Aswin
.
Nanoscale CMOS VLSI Circuits: Design for Manufacturability
.
US
: McGraw-Hill Professional, 2010.
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Nanoscale CMOS VLSI Circuits: Design for Manufacturability
Authors:
Sandip Kundu
and
Aswin Sreedhar
Published:
June 2010
eISBN:
9780071635202 0071635203
|
ISBN:
9780071635196
Open eBook
Book Description
Table of Contents
Contents
Preface
1 Introduction
Technology Trends: Extending Moore’s Law
Device Improvements
Contributions from Material Science
Deep Subwavelength Lithography
Design for Manufacturability
Value and Economics of DFM
Variabilities
The Need for a Model-Based DFM Approach
Design for Reliability
Summary
References
2 Semiconductor Manufacturing
Introduction
Patterning Process
Photolithography
Etching Techniques
Optical Pattern Formation
Illumination
Diffraction
Imaging Lens
Exposure System
Aerial Image and Reduction Imaging
Resist Pattern Formation
Partial Coherence
Lithography Modeling
Phenomenological Modeling
Fully Physical Resist Modeling
Summary
References
3 Process and Device Variability: Analysis and Modeling
Introduction
Gate Length Variation
Patterning Variations Due to Photolithography
Line Edge Roughness: Theory and Characterization
Gate Width Variation
Atomistic Fluctuations
Thickness Variation in Metal and Dielectric
Stress-Induced Variation
Summary
References
4 Manufacturing-Aware Physical Design Closure
Introduction
Control of the Lithographic Process Window
Resolution Enhancement Techniques
Optical Proximity Correction
Subresolution Assist Features
Phase Shift Masking
Off-Axis Illumination
Physical Design for DFM
Geometric Design Rules
Restrictive Design Rules
Model-Based Rules Check and Printability Verification
Manufacturability-Aware Standard Cell Design
Mitigating the Antenna Effect
Placement and Routing for DFM
Advanced Lithographic Techniques
Double Patterning
Inverse Lithography
Other Advanced Techniques
Summary
References
5 Metrology, Manufacturing Defects, and Defect Extraction
Introduction
Process-Induced Defects
Classification of Error Sources
Defect Interaction and Electrical Effects
Modeling Particle Defects
Layout Methods to Improve Critical Area
Pattern-Dependent Defects
Pattern-Dependent Defect Types
Pattern Density Problems
Statistical Approach to Modeling Patterning Defects
Layout Methods That Mitigate Patterning Defects
Metrology
Precision and Tolerance in Measurement
CD Metrology
Overlay Metrology
Other In-Line Measurements
In-Situ Metrology
Failure Analysis Techniques
Nondestructive Techniques
Destructive Techniques
Summary
References
6 Defect Impact Modeling and Yield Improvement Techniques
Introduction
Modeling the Impact of Defects on Circuit Behavior
Defect-Fault Relationship
Role of Defect-Fault Models
Test Flow
Yield Improvement
Fault Tolerance
Fault Avoidance
Summary
References
7 Physical Design and Reliability
Introduction
Electromigration
Hot Carrier Effects
Hot Carrier Injection Mechanisms
Device Damage Characteristics
Time-Dependent Dielectric Breakdown
Mitigating HCI-Induced Degradation
Negative Bias Temperature Instability
Reaction-Diffusion Model
Static and Dynamic NBTI
Design Techniques
Electrostatic Discharge
Soft Errors
Types of Soft Errors
Soft Error Rate
SER Mitigation and Correction for Reliability
Reliability Screening and Testing
Summary
References
8 Design for Manufacturability: Tools and Methodologies
Introduction
DFx in IC Design Flow
Standard Cell Design
Library Characterization
Placement, Routing, and Dummy Fills
Verification, Mask Synthesis, and Inspection
Process and Device Simulation
Electrical DFM
Statistical Design and Return on Investment
DFM for Optimization Tools
DFM-Aware Reliability Analysis
DFx for Future Technology Nodes
Concluding Remarks
References
Index